Bit Line Sense Circuit Layout for DRAM 2-Bit Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic Random Access Memory (DRAM) arrays face issues with 2-bit errors due to capacitor defects, which exceed the error correcting capability of existing Error Correcting Codes (ECC), leading to reading errors.
Innovation Solution
A bit line sense circuit design that divides adjacent storage units into groups, connecting them to different sense amplifier groups, allowing 2-bit errors to be detected and corrected as separate 1-bit errors using existing ECC capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC is used for error correction in DRAM, then 1-bit errors can be corrected, but 2-bit errors cannot be corrected
Solution Approach 1:
The patent divides the storage array into multiple banks, where each bank is independently managed by its own sense amplifier group. This segmentation allows errors to be isolated within specific banks, enabling the ECC to handle 2-bit errors as two separate 1-bit errors in different banks, thereby improving error correction capability without increasing overall ECC complexity
2Device complexity
If adjacent storage units are connected to the same sense amplifier, then circuit complexity is reduced, but 2-bit errors cannot be detected and corrected
Solution Approach 1:
The patent segments the storage units into different banks, with each bank connected to a dedicated sense amplifier group. This segmentation ensures that adjacent storage units are distributed across different banks, allowing 2-bit errors to be detected as separate events in different banks while maintaining manageable circuit complexity through systematic organization
Solution Approach 2:
The patent introduces bank-level addressing and control mechanisms as intermediaries between the storage units and sense amplifiers. This intermediary layer enables the system to track which bank each storage unit belongs to, allowing the ECC to identify and correct 2-bit errors by recognizing they occurred in different banks, without requiring direct complex interconnections between all sense amplifiers
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups. According to the technical solution, two adjacent bit lines are connected to different sense amplifier groups, and when read errors occur simultaneously on the two adjacent bit lines, error data may be detected and corrected by an Error Correcting Code (ECC).