Bit Line Sensing System Compensating for Resistance Variations
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Solution Overview
Problem
Memory devices face challenges in reading memory cells due to variations in bit line resistance, which increase with the length of the bit line between the sensing circuit and the active block of memory cells, leading to delayed voltage sensing and incorrect data sampling.
Innovation Solution
A bit line sensing system that adjusts the bit line clamp voltage as a function of the bit line length, using a Clamp Voltage Generator to determine the initial and final clamp voltages based on the block address, ensuring consistent voltage discharge regardless of the active block's location, and optionally varying the sensing time to compensate for distance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bit line length increases to accommodate larger memory arrays, then the memory capacity increases, but the bit line resistance increases causing delayed voltage sensing and read errors
Solution Approach 1:
The patent changes the clamp voltage parameter dynamically based on the active block location. When a block farther from the sensing circuit is activated, a higher clamp voltage is applied to compensate for increased bit line resistance, ensuring consistent voltage discharge timing and accurate reading across the entire memory array
Solution Approach 2:
The sensing system transitions from a static clamp voltage approach to a dynamic one where the clamp voltage is adjusted in real-time based on which block is active. This dynamic adaptation allows the system to maintain optimal sensing conditions regardless of the physical location of the active memory block
2Quantity of substance
If the bit line length increases to accommodate larger memory arrays, then the memory capacity increases, but the read time increases due to slower voltage discharge
Solution Approach 1:
By adjusting the clamp voltage parameter based on block location, the patent equalizes the discharge time constant across different bit line lengths. This allows all blocks to be read in the same time regardless of their distance from the sensing circuit, maintaining high read speed while supporting large memory capacity
Solution Approach 2:
The clamp voltage is pre-adjusted based on the known active block location before the read operation begins. This preliminary compensation ensures that the voltage discharge occurs at the correct rate from the start, eliminating delays that would otherwise occur during the sensing process
3Device complexity
If a fixed clamp voltage is used for all blocks, then the device complexity is reduced, but the reading accuracy varies with block location
Solution Approach 1:
The sensing circuit incorporates dynamic control logic that selects the appropriate clamp voltage based on the active block address. This adds moderate complexity to the control mechanism but maintains simplicity in the core sensing circuitry, achieving high reading accuracy without significantly increasing overall device complexity
Solution Approach 2:
Different clamp voltage levels are applied locally depending on which block is active. The control system identifies the active block location and applies the appropriate voltage level from a set of predefined values, ensuring each block receives the optimal clamp voltage for accurate reading
Data Source
AI summary
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.