Bit-Line Settling Time Management in Non-Volatile Memory
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Solution Overview
Problem
In semiconductor memory systems, the bit line settling time is crucial for accurate sensing operations, but capacitive coupling between bit lines can slow down voltage stabilization, leading to inaccuracies in read and program verify operations, especially when dealing with non-contiguous sets of bit lines.
Innovation Solution
Managing bit line settling time by using different settling times based on the configuration of bit lines, with longer times for non-contiguous sets to ensure accurate sensing and reduce the number of program loops required for programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a uniform bit line settling time is used for all bit lines, then the system operation is simplified, but sensing accuracy deteriorates when dealing with non-contiguous sets of bit lines due to capacitive coupling effects
Solution Approach 1:
The patent applies local quality by differentiating bit line settling times based on the contiguity of bit line sets. Non-contiguous bit line sets (where capacitive coupling occurs) are assigned longer settling times, while contiguous sets use standard settling times. This localized adjustment resolves the contradiction by maintaining sensing accuracy for problematic configurations without complicating the overall system operation.
Solution Approach 2:
The patent changes the time parameter dynamically based on bit line configuration characteristics. By detecting whether a set of bit lines is contiguous or non-contiguous, the system adjusts the settling time parameter accordingly, thereby maintaining measurement precision without requiring complex operational procedures.
2Speed
If capacitive coupling between bit lines is present, then bit line voltage stabilization is slowed, but the physical structure of adjacent bit lines cannot be changed
Solution Approach 1:
The patent applies preliminary anti-action by anticipating the capacitive coupling effect and compensating for it in advance. When non-contiguous bit line sets are detected, the system proactively extends the settling time to allow sufficient voltage stabilization, counteracting the harmful capacitive coupling effect before it degrades sensing accuracy.
Solution Approach 2:
The patent converts the harmful capacitive coupling effect into a detectable condition that triggers a beneficial response. By identifying non-contiguous bit line configurations (where coupling occurs), the system applies extended settling times that ensure accurate sensing, thereby transforming the potential harm into a managed parameter.
3Measurement precision
If longer bit line settling times are used for non-contiguous sets, then sensing accuracy is improved, but programming time increases
Solution Approach 1:
The patent applies partial action by extending the settling time only when necessary - specifically for non-contiguous bit line sets where capacitive coupling degrades accuracy. Contiguous bit line sets continue to use standard settling times, thereby minimizing the overall time loss while maintaining sensing accuracy where it is critically needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the accuracy of sensing operations and reduces the number of program loops needed, enhancing the overall efficiency and reliability of memory cell programming.
Implementation Method 1
capacitive coupling between the bit lines may impact the voltages applied to the bit lines
Data Source
AI summary
A non-volatile memory system comprises a plurality of word lines, a plurality of bit lines, non-volatile memory cells, and a sensing circuit. The sensing circuit is configured to sense a first set of the memory cells coupled to a contiguous set of the bit lines and a selected word line using a first bit line settling time. The sensing circuit is configured to sense a second set of the memory cells coupled to a non-contiguous set of the bit lines and the selected word line using a second bit line settling time.