Bit Line Shield Structure to Prevent Oxidation in Memory Cells

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Solution Overview

Problem

Semiconductor memory devices face challenges in maintaining high integration while ensuring electrical characteristics and reliability due to factors such as miniaturization and high-speed, low-power consumption requirements, which can lead to deteriorated electrical performance.

Innovation Solution

The semiconductor memory device incorporates a shield pattern positioned lower than the bit line capping pattern, composed of materials like polysilicon and silicon oxide, to mitigate oxidation of the bit line metal and enhance electrical reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If high integration is implemented to meet high-speed and low-power consumption requirements, then operating speed and power consumption are improved, but electrical characteristics and reliability deteriorate

Engineering Contradiction:
Improvepower consumptionVSAvoidelectrical reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

A shield pattern made of polysilicon is introduced as an intermediary layer between the bit line and the surrounding environment. This shield pattern acts as a mediator that prevents direct interaction between oxygen and the bit line metal, thereby maintaining electrical reliability while allowing high integration for low-power operation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If high integration is implemented, then device functionality is improved, but metal oxidation of bit line increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidmetal oxidation
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The shield pattern is formed in advance before the bit line is fully exposed to oxidizing conditions. By establishing this protective polysilicon layer beforehand, the bit line is pre-protected from oxidation that would otherwise occur during subsequent processing and operation, allowing high integration without compromising metal integrity

Inventive Principle:
Principle #9Preliminary anti-action

3Ease of manufacture

If device miniaturization is pursued, then manufacturing cost is reduced, but electrical characteristics deteriorate

Engineering Contradiction:
Improvemanufacturing costVSAvoidelectrical characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Instead of uniformly protecting all structures, the shield pattern is selectively applied only to the bit line regions that require protection from oxidation. This localized approach maintains the benefits of miniaturization and cost reduction while specifically addressing the electrical characteristic deterioration in critical areas

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The shield pattern effectively reduces metal oxidation, improving the electrical characteristics and reliability of the semiconductor memory device by maintaining the integrity of the bit line structure.

Implementation Method 1

The shield pattern may include at least one of polysilicon, silicon oxide, or a combination thereof. The shield pattern effectively reduces metal oxidation

Methodology Applied
Scientific EffectOxidation prevention: Oxidation

Data Source

PatentUS12453083B2Semiconductor memory device and method of forming the same
Publication Date: 2025.10.21 SAMSUNG ELECTRONICS CO LTD
  • US12453083B2 patent drawing
  • US12453083B2 patent drawing
  • US12453083B2 patent drawing

AI summary

A semiconductor memory device including an active pattern defined by a device isolation pattern, a bit line extending in a first direction on the device isolation pattern and the active pattern, a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line, and a shield pattern covering one side of the bit line may be provided. An upper surface of the shield pattern may be at a height lower than an upper surface of the first capping pattern.