Semiconductor Bit Line Structure With Controlled Silicide Diffusion
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Solution Overview
Problem
In traditional gate-all-around transistor manufacturing, it is difficult to accurately control the diffusion range of the metal silicide layer, leading to small diffusion ranges that cause connection issues and uneven bit line surfaces, resulting in high resistance.
Innovation Solution
A method involving the formation of trenches with initial source-drain regions, protective dielectric layers, and conductive material layers to create bit line structures with a flat surface, reducing resistance and increasing contact area, which includes thinning the source-drain regions and depositing metal silicide layers to form bit lines that extend along a direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal material is deposited at the bottom of each word-line trench and annealed into metal silicide layer, then bit line structure is formed, but the diffusion range of metal silicide layer cannot be accurately controlled causing connection issues
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer at the bottom of the trench before depositing the metal silicide layer. This sacrificial layer pre-establishes a controlled diffusion barrier that prevents uncontrolled diffusion during annealing, thereby ensuring accurate diffusion range control and reliable connections between adjacent bit lines.
Solution Approach 2:
The patent uses a sacrificial layer as an intermediary between the substrate and the metal silicide layer. This intermediary layer controls the diffusion process by providing a defined interface that limits metal silicide diffusion into the substrate, preventing both excessive diffusion and insufficient connection.
2Reliability
If metal silicide layer is formed by traditional annealing process, then bit line structure is created, but the surface becomes uneven resulting in high resistance
Solution Approach 1:
The patent performs preliminary planarization by forming the sacrificial layer and performing CMP (chemical mechanical polishing) before depositing the metal silicide layer. This preliminary action creates a flat surface foundation that ensures uniform metal silicide layer deposition and prevents surface unevenness that would cause high resistance.
Solution Approach 2:
The patent changes the physical state and surface parameters by using CMP processing to achieve atomic-level flatness of the sacrificial layer surface before metal deposition. This parameter change in surface flatness directly translates to uniform metal silicide layer formation and low resistance electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves bit line quality, reduces resistance, and decreases RC delay by ensuring a larger contact area and a flat surface for the bit line structures, enhancing the semiconductor structure's performance.
Implementation Method 1
a metal material is deposited at the bottom of each word-line trench, and then is annealed into a metal silicide layer. The metal silicide layer diffuses to a range in the base
Implementation Method 2
depositing a conductive material layer at two opposite sides of the first initial source-drain region, to form bit line structures
Data Source
AI summary
The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.