Semiconductor Memory Bit Line Structure With Silicon Protection Layer
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Solution Overview
Problem
The complexity of manufacturing processes for MOS transistors in DRAM memory cells and other regions within the same chip poses challenges in integrating these processes effectively, due to differing structural designs and density requirements.
Innovation Solution
A semiconductor memory device and manufacturing method where a first silicon layer is interposed between a first metal layer and a bit line capping layer, protecting the metal layer from damage during the formation of a metal silicide layer, and allowing for the simultaneous formation of bit line and gate structures using a shared multilayer stack process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit line structure with metal layer and capping layer is formed, then electrical connection is achieved, but the metal layer is damaged during metal silicide layer formation
Solution Approach 1:
A silicon layer is introduced as an intermediary between the metal layer and the metal silicide layer. This silicon layer acts as a protective barrier that prevents direct contact and potential damage between the metal layer and the silicidation process, while still allowing the formation of the metal silicide layer on the silicon layer surface.
2Adaptability or versatility
If MOS transistors in memory cells and other regions have different structural designs, then product specifications and density requirements are met, but manufacturing process complexity increases
Solution Approach 1:
The bit line structure with the silicon layer is designed to be universally applicable across different regions of the semiconductor device. The same silicon layer protection approach can be used for both memory cell MOS transistors and other region transistors, even though their structural designs differ, thereby simplifying the manufacturing process while maintaining adaptability to different product specifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, enhances electrical performance, and increases product yield by protecting the metal layers and enabling integrated processing of bit line and gate structures.
Implementation Method 1
the first silicon layer is used to protect the first metal layer from being damaged by the process of forming a metal silicide layer
Data Source
AI summary
A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.