Bit Line Direct Contact Structure With SiOx Passivation
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Solution Overview
Problem
As integrated circuit devices are downscaled, the reduction in contact size leads to increased contact resistance, impairing electrical performance and reliability due to the smaller electrical contacts.
Innovation Solution
The integration of a substrate with a bit line having a lower and upper conductive pattern, a direct contact, a spacer structure on both sidewalls of the bit line, and a field passivation layer between the direct contact and the spacer structure, which includes a nonstoichiometric silicon oxide layer to reduce contact resistance and enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integrated circuit devices are downscaled to reduce size, then device integration and miniaturization are improved, but contact resistance increases due to smaller electrical contacts
Solution Approach 1:
The bit line is divided into multiple conductive patterns (lower conductive pattern and upper conductive pattern) stacked vertically. This segmentation allows the bit line to maintain smaller footprint area while preserving adequate conductive cross-section, thereby reducing contact resistance despite device downsaling.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure. By adding the vertical dimension with multiple conductive patterns stacked above each other, the bit line achieves both miniaturization in planar area and maintained or reduced contact resistance through increased vertical conductive path area.
2Productivity
If electrical contact size is reduced for higher integration, then device integration is improved, but contact resistance increases impairing electrical performance
Solution Approach 1:
The bit line is segmented into multiple conductive patterns stacked vertically, allowing higher integration density in the planar direction while maintaining adequate total conductive area in the vertical dimension to preserve electrical performance and reduce contact resistance.
Solution Approach 2:
The bit line employs a composite structure with multiple conductive patterns made of conductive materials stacked together. This composite approach increases the effective conductive cross-section without increasing planar footprint, thereby reducing contact resistance while achieving higher integration density.
3Length of moving object
If contact dimensions are reduced for miniaturization, then device size is reduced, but charge trapping and depletion occur increasing contact resistance
Solution Approach 1:
By transitioning to a three-dimensional stacked structure with multiple conductive patterns, the invention reduces contact dimension in the planar direction while compensating for the reduced contact area by increasing the vertical conductive path area, thereby preventing charge trapping and depletion effects.
Solution Approach 2:
The invention changes the geometric parameters of the bit line from a single planar layer to multiple stacked layers, altering the distribution of electric field and charge density. This parameter change prevents charge trapping and depletion at the contact interface by distributing the electrical stress across multiple conductive patterns.
Data Source
AI summary
An integrated circuit device includes a substrate having an active area therein, a bit line on the substrate, and a direct contact, which extends between the active area and the bit line and electrically couples the bit line to a portion of the active area. A spacer structure is also provided, which extends on sidewalls of the bit line and on sidewalls of the direct contact. A field passivation layer is provided, which extends between the sidewalls of the direct contact and the spacer structure. The spacer structure and the field passivation layer may include different materials, and the field passivation layer may directly contact the sidewalls of the direct contact. The field passivation layer can include nonstoichiometric silicon oxide SiOx, where 0.04≤x≤0.4, and may have a thickness of less than about 25 Å.