Bit Line Spacer Structure for High-Rate Sacrificial Layer Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the removal of sacrificial layers, which can inadvertently remove the spacer of the bit line structure, compromising its stability due to the high etching rate of the etchant used.
Innovation Solution
A method involving the formation of a first and second spacer on the bit line structure, with a photoresist layer in the trench, controlled etching to expose the top surface of the second spacer, and subsequent formation of a third spacer to protect the second spacer during subsequent etching processes, ensuring stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high etching rate etchant is used to remove the sacrificial layer, then the productivity is improved, but the spacer of the bit line structure is removed, worsening the stability of the bit line structure
Solution Approach 1:
The spacer structure is divided into multiple segments: a first spacer, a second spacer, and a third spacer. Each spacer serves as a protective layer for the others during the etching process. The first spacer is formed initially, then the second spacer is formed on top of it, allowing selective removal of the second spacer to expose the first spacer. Finally, the third spacer is formed to protect both previous spacers during the high-rate etching of the sacrificial layer.
Solution Approach 2:
The first, second, and third spacers are formed in advance before the sacrificial layer removal process. These spacers are prepared as protective structures that will shield the bit line structure during the subsequent high-rate etching process. The preliminary formation of these protective spacers enables the use of aggressive etching conditions without damaging the bit line structure.
2Reliability
If the spacer is protected by multiple layers, then the stability of the bit line structure is improved, but the device complexity increases
Solution Approach 1:
The second spacer is selectively removed in a controlled manner to expose the first spacer. This extraction of the second spacer creates a stepped structure where the first spacer remains as a protective layer. The selective removal is achieved by etching through the second spacer while leaving the first spacer intact, thereby simplifying the structure for the final etching step while maintaining protection during intermediate stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the stability of the bit line structure by protecting the second spacer from high-etching-rate processes, maintaining structural integrity during sacrificial layer removal.
Implementation Method 1
The photoresist layer is removed to expose a bottom surface of the trench
Implementation Method 2
the sacrificial layer is removed by a wet etching process
Implementation Method 3
the sacrificial layer is polished by a chemical mechanical planarization process
Data Source
AI summary
The present disclosure provides a manufacturing method of a semiconductor structure. A bit line structure and a trench adjacent to the bit line structure are provided, wherein a first spacer is disposed on a sidewall and a top surface of the bit line structure, and a second spacer is disposed on a sidewall and a top surface of the first spacer. A photoresist layer is formed in the trench, wherein the photoresist layer has a height that is smaller than a depth of the trench. A portion of the second spacer is removed, wherein the etched second spacer has a height that is substantially equal to the height of the photoresist layer. The photoresist layer is removed. A third spacer is formed on a sidewall of the etched second spacer, wherein the third spacer covers a top surface of the etched second spacer.