Bit Line Switches for 3D Memory RC Delay Reduction
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Solution Overview
Problem
The RC delay in bit lines of memory devices significantly contributes to the total sense time and programming time, limiting the operating speed of three-dimensional memory devices, such as those with vertical NAND strings.
Innovation Solution
Incorporating bit line switches to reduce RC delay, these switches are integrated into the three-dimensional memory device structure to improve operational speed by managing electrical connections and disconnections efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit line switches are incorporated to reduce RC delay, then operating speed is improved, but device complexity increases
Solution Approach 1:
The bit line is divided into multiple segments with individual switches controlling each segment. This segmentation allows selective activation of only the necessary bit line portions during read/write operations, reducing the effective RC delay for active segments while maintaining the ability to address the entire memory array through coordinated switch control.
Solution Approach 2:
The bit line switches are dynamically controlled to change their conductive state based on operation requirements. During read/write operations, specific switches are activated to create low-impedance paths only where needed, dynamically optimizing the RC characteristics. The switches remain inactive during other operations, adapting the circuit behavior to current operational needs.
2Loss of time
If bit line switches are used to manage electrical connections, then sense time is reduced, but manufacturing complexity increases
Solution Approach 1:
The bit line switches serve as intermediary elements between the sense amplifier and the memory cell arrays. These switches act as controlled connectors that can rapidly transition between conductive and non-conductive states, enabling fast connection/disconnection of bit line segments during sense operations. This intermediary function reduces the time required to establish proper electrical connections for sensing while isolating the complexity of switch control from the core sensing circuitry.
Data Source
AI summary
A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.