Bit Line Switches for Memory Array Edge Space Reduction
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Solution Overview
Problem
Conventional memory devices with complimentary, double-ended sense amplifiers face challenges in reducing memory array size due to unused digit lines at the edges, leading to wasted space on the semiconductor die.
Innovation Solution
The implementation of bit line switches that provide conductive coupling between bit lines of single-ended and double-ended sense amplifiers, allowing for dynamic reconfiguration of bit line connections during threshold voltage compensation and sense operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated reference digit lines are used at the edges of the memory array, then reference voltage level is provided for better distinction of read/write values, but the size of the memory array increases
Solution Approach 1:
Bit lines at the edges of the memory array are configured to serve dual purposes: acting as data bit lines during normal read/write operations and as reference digit lines during threshold voltage compensation operations. This multi-functionality eliminates the need for dedicated reference digit lines, thereby maintaining measurement precision while reducing memory array size
Solution Approach 2:
The system dynamically reconfigures the function of edge bit lines through controlled activation and deactivation by bit line switches. During threshold voltage compensation, edge bit lines are activated as reference digit lines; during normal operations, they function as data bit lines. This dynamic switching allows the same physical infrastructure to serve multiple functions, reducing overall memory array size
2Adaptability or versatility
If bit line switches are added to enable dynamic reconfiguration, then efficient use of edge bit lines is achieved, but device complexity increases
Solution Approach 1:
Bit line switches are selectively placed only at the edges of the memory array where bit lines need to be reconfigured, rather than throughout the entire array. This localized approach provides the necessary adaptability for edge bit line utilization while minimizing the overall number of switches and associated complexity
Solution Approach 2:
The control logic for bit line switches is integrated with the existing sense amplifier control mechanisms. The same control circuitry that manages sense amplifier operations also controls the activation and deactivation of bit line switches, merging multiple control functions into a unified system and reducing overall device complexity
Data Source
AI summary
Apparatus and methods for providing a conductive path between bit lines using bit line switches are disclosed. An example apparatus includes a memory mat comprising a first plurality of bit lines and a second plurality of bit lines. A plurality of bit line switches can be activated to provide a conductive path between respective ones of the first plurality of bit lines and a second plurality of bit lines. For example, the bit line switches can be activated during a threshold voltage compensation phase or operation and deactivated during a memory cell activation phase or operation.