Bit Line Timing for Fast, Precise Non-Volatile Memory Programming

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Solution Overview

Problem

Existing non-volatile memory devices face challenges in accurately programming threshold voltage ranges, leading to wide distributions and inefficiencies in programming time.

Innovation Solution

The implementation of a control mechanism that applies program pulses with divided phases and adjusts bit line voltages based on the threshold voltage of memory cells, using a stepped-up level to optimize programming speed and distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional programming methods are used to program non-volatile memory cells, then the programming process is simple, but the threshold voltage distribution becomes wide and programming accuracy deteriorates

Engineering Contradiction:

Improvethreshold voltage programming accuracyVSAvoidprogramming process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The programming process is segmented into multiple phases within each program pulse, with different bit line voltage levels applied to different memory cells based on their programming status. This segmentation allows simultaneous fast programming for cells needing more pulses and slow programming for cells approaching target threshold voltage, resolving the contradiction between programming speed and threshold voltage distribution width.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bit line voltage level is dynamically adjusted based on the count of program pulses applied to each memory cell. As cells approach their target threshold voltage, the system transitions from fast programming mode to slow programming mode by changing bit line voltage, enabling adaptive control that maintains narrow threshold voltage distributions while programming multiple cells in parallel.

Inventive Principle:

Principle #15Dynamics

2Productivity

If fast programming mode is used for all memory cells, then programming speed increases, but threshold voltage distribution becomes wide and programming precision deteriorates

Engineering Contradiction:

Improveprogramming speedVSAvoidthreshold voltage distribution width

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

Different bit line voltage levels are applied to different memory cells based on their individual programming status. Cells in fast programming mode receive higher bit line voltages for rapid threshold voltage increase, while cells in slow programming mode receive lower bit line voltages for precise threshold voltage control, achieving both high speed and high precision simultaneously across the memory array.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The bit line voltage parameter is changed based on the program pulse count for each memory cell. By monitoring how many pulses have been applied and adjusting the bit line voltage accordingly, the system transitions between fast and slow programming modes, maintaining narrow threshold voltage distributions while maximizing overall programming speed.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If slow programming mode is used for all memory cells, then threshold voltage distribution remains narrow, but programming time increases significantly

Engineering Contradiction:

Improvethreshold voltage distribution widthVSAvoidprogramming time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The programming process uses periodic verify operations to check whether memory cells have reached their target threshold voltage. Based on the verify results and pulse count, the system periodically transitions cells between fast and slow programming modes, achieving narrow threshold voltage distributions while minimizing overall programming time through this periodic monitoring and adaptive switching.

Inventive Principle:

Principle #19Periodic action

4Productivity

If the same bit line voltage level is applied to all memory cells, then the control circuitry is simple, but programming efficiency decreases when cells have different programming needs

Engineering Contradiction:

Improveprogramming efficiencyVSAvoidcontrol circuitry complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system preliminarily determines the programming status of each memory cell by tracking the number of program pulses applied and monitoring threshold voltage levels during verify operations. Based on this preliminary assessment, the control circuitry pre-positions cells into appropriate programming modes by adjusting bit line voltages before subsequent program pulses, maximizing programming efficiency without requiring complex real-time control during each pulse.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12580023B2Bit line timing based cell tracking quick pass write for programming non-volatile memory apparatuses

Publication Date: 2026.03.17 SANDISK TECHNOLOGIES LLC

AI summary

A memory apparatus includes memory cells connected to word lines and configured to store a threshold voltage corresponding to data states. The memory cells are disposed in memory holes coupled to bit lines. A control means applies program pulses to selected ones of the word lines. The control means determines when the threshold voltage of each of the memory cells exceeds a lower verify level of one of the data states targeted and maintains a respective count of a number of the program pulses subsequently applied thereto before reaching a lockout state. Each of the program pulses is divided into phases. The control means sets a voltage of one of the bit lines coupled to each of the memory cells at a stepped up level as a function of the respective count and according to each of the phases in which the voltage is set to the stepped up level.