Bit Line Transistor Area Reduction via Array Cell Copying
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Solution Overview
Problem
Conventional bit line transistors in memory cell arrays occupy large circuit layout areas due to the limitations of metal-oxide semiconductor (MOS) transistor manufacturing processes and contact holes.
Innovation Solution
Replacing conventional MOS transistors with array cells that utilize global and local bit lines, bit line transistor control lines, and fixed value memory cells to form bit line transistors, allowing for reduced circuit layout area by interlacing these components and removing data storage layers to create bit line transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional MOS transistors are used for bit line transistors, then the transistor can be manufactured using standard MOS processes, but the circuit layout area occupied by the bit line transistor becomes large
Solution Approach 1:
The patent creates a copy of a memory cell structure to function as a bit line transistor. Instead of using a conventional MOS transistor, the invention fabricates a transistor using the same array cell fabrication process by programming a selected array cell to have a very high threshold voltage (greater than 10V), effectively creating a transistor copy that serves the bit line selection function while occupying minimal layout area.
Solution Approach 2:
The patent makes the array cell structure universal by enabling it to serve dual functions: normal data storage when programmed with standard threshold voltages, and bit line transistor functionality when programmed with very high threshold voltages. This multi-functionality eliminates the need for separate MOS transistor structures, thereby reducing overall circuit layout area.
2Area of stationary object
If array cells are used to replace MOS transistors for bit line transistors, then the circuit layout area is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent resolves manufacturing complexity by changing the programming parameter (threshold voltage) rather than the fabrication process itself. The same array cell structure is manufactured using standard processes, but by applying different programming voltages, the threshold voltage can be adjusted to create either a normal memory cell or a bit line transistor, thereby maintaining manufacturing simplicity while achieving area reduction.
Data Source
AI summary
A memory device comprises a main memory array having a plurality of bit lines, and a select array having a plurality of transistors coupled to the bit lines. Wherein one of the plurality of transistors is electrically programmed to a threshold voltage greater than a threshold voltage of another one of the plurality of transistors.