Bit Line Trench Intrusion for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices become more integrated, the reduced thickness of interlayer insulation between storage node contacts and bit line contacts increases the probability of electrical shorts and parasitic capacitance, leading to reliability and performance issues.
Innovation Solution
The implementation of a bit line structure disposed in a trench pattern that intrudes into the side of the storage node contact plug, combined with an insulation layer and potentially air gaps, to enhance electrical insulation and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of interlayer insulation layer is reduced to increase integration, then the number of storage node contacts and bit line contacts integrated in a limited area is increased, but the probability of electrical short between adjacent contacts increases and parasitic capacitance increases
Solution Approach 1:
The patent introduces a trench structure that intrudes into the side of the storage node contact plug, creating a three-dimensional spatial separation between the bit line contact and storage node contact. This vertical and lateral intrusion into the side wall provides additional insulation distance without increasing the planar footprint, thereby maintaining high integration density while improving electrical insulation reliability
Solution Approach 2:
The patent introduces an air gap as an intermediary substance between the bit line contact and storage node contact. This air gap acts as a dielectric medium with lower permittivity than solid insulation materials, reducing parasitic capacitance while providing electrical isolation. The air gap is created by the trench intrusion and subsequent filling process, serving as a mediator that resolves the conflict between close spacing and electrical isolation
2Area of stationary object
If the thickness of interlayer insulation layer is reduced, then device area is reduced, but parasitic capacitance value between conductive lines increases
Solution Approach 1:
The patent changes the dielectric parameter by introducing an air gap with lower permittivity between the conductive lines. By replacing solid insulation material with air (or vacuum) in the trench region, the parasitic capacitance is reduced while maintaining the same physical spacing. This parameter change allows for reduced device area without increasing parasitic capacitance, as the air gap provides electrical isolation with minimal capacitive coupling
3Ease of manufacture
If conventional insulation structures are used, then manufacturing process is simple, but electrical insulation characteristics between storage node contact and bit line contact are insufficient
Solution Approach 1:
The patent segments the insulation structure by creating a trench that divides the space between storage node contact and bit line contact. This segmentation separates the insulation function into two parts: the original interlayer insulation layer and the additional trench insulation structure. The trench is formed by selective etching and filling processes that target specific regions, providing enhanced insulation where needed while maintaining simple manufacturing elsewhere in the device
Data Source
AI summary
Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.