Bit Line Verify Bias for Neighbor Word Line Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The shrinking size of memory circuitry in non-volatile semiconductor memory devices leads to increased neighbor word line interference (NWI), causing degraded threshold voltage margin and widened Vth distribution, which complicates efficient programming and data retention, especially in narrow ON pitch memory cells.
Innovation Solution
A memory apparatus and method that dynamically adjusts bit line voltage biases during program verify operations based on comparisons between adjacent memory cells, compensating for neighbor word line interference by determining appropriate bit line voltage biases for memory cells connected to selected and neighboring word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory circuitry size is shrunk to increase storage density, then storage capacity is improved, but neighbor word line interference increases causing degraded threshold voltage margin
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bit line voltage bias based on the data states of neighboring word lines. When neighboring cells are in high states, a first bit line voltage bias is applied; when in low states, a second bit line voltage bias is applied. This dynamic parameter adjustment compensates for the increased interference caused by shrunk memory circuitry while maintaining storage density improvements.
2Quantity of substance
If memory circuitry size is shrunk to increase storage density, then storage capacity is improved, but Vth distribution widens complicating programming
Solution Approach 1:
The patent uses parameter changes to address widened Vth distribution by implementing dynamic bit line voltage bias adjustment. The control circuit selects different voltage biases based on neighboring cell states, which compensates for the interference-induced Vth shifts and narrows the effective distribution, simplifying programming operations despite increased storage density.
3Reliability
If dynamic bit line voltage bias is applied to compensate for neighbor word line interference, then threshold voltage stability is improved, but control complexity increases
Solution Approach 1:
The patent applies preliminary action by determining the data states of neighboring word lines before performing the verify operation on the target word line. This advance knowledge allows the control circuit to pre-select the appropriate bit line voltage bias, compensating for interference effects before they impact threshold voltage measurement, thereby improving stability while managing control complexity through proactive rather than reactive control.
4Reliability
If neighbor word line interference is compensated by bit line voltage adjustment, then data retention is improved, but operation time increases
Solution Approach 1:
The patent uses preliminary action to determine neighboring cell states before the verify operation, enabling immediate selection of the correct bit line voltage bias without iterative adjustments. This approach improves data retention by ensuring proper compensation from the start, while minimizing operation time by avoiding multiple verification cycles that would be needed with fixed voltage bias approaches.
Data Source
AI summary
A memory apparatus is provided and includes memory cells connected to word lines and coupled to bit lines and configured to retain a threshold voltage corresponding to data states. A control means determines ones of the data states for a first set of the memory cells connected to a selected word line and for a second set of the memory cells connected to at least one neighboring word line. The control means determines which of a plurality of state groups the memory cells of the first and second sets belong according to the data states determined. The control means determines which one of a plurality of bit line voltage biases to be applied to the bit lines coupled to the memory cells of the first set during a verify operation based on a comparison of state groups of the memory cells of the first set and the second set.