Bit Line Insulator Layout for Lower Via Parasitic Capacitance
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Solution Overview
Problem
The increasing parasitic capacitance between lines and via contacts in three-dimensional memory cell arrays of semiconductor storage devices, such as NAND flash memory, due to the narrowing of intervals between adjacent lines, poses a challenge that affects the performance and scalability of these devices.
Innovation Solution
The implementation of insulating films with varying materials and structures, such as silicon nitride and silicon oxynitride films, is used to reduce parasitic capacitance by altering the geometry and material properties of bit lines and via contacts, thereby minimizing capacitance and allowing for narrower line intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the interval between adjacent lines is narrowed to achieve downscaling of memory cell array, then the density and capacity of the semiconductor storage device are improved, but the parasitic capacitance between lines and via contacts increases
Solution Approach 1:
The patent applies different insulating materials with different dielectric constants to different regions around the via contact. Specifically, a first insulating material with lower dielectric constant is placed in the region closer to the via contact, while a second insulating material with higher dielectric constant is placed in the region farther from the via contact. This local differentiation of material properties reduces parasitic capacitance near the via contact while maintaining appropriate insulation elsewhere, thereby resolving the contradiction between line interval narrowing and parasitic capacitance reduction.
Solution Approach 2:
The patent employs a composite insulating structure consisting of multiple insulating layers with different materials and dielectric constants. This composite structure allows optimization of the electrical characteristics by combining materials with complementary properties, enabling reduced parasitic capacitance while maintaining the necessary insulation performance for scaled-down line intervals.
2Length of moving object
If insulating films with varying materials and structures are implemented to reduce parasitic capacitance, then the line interval can be narrowed, but the device complexity and manufacturing process complexity increase
Solution Approach 1:
The insulating film is segmented into multiple layers with different materials and thicknesses. The first insulating film is positioned closer to the via contact with specific material properties, while the second insulating film is positioned farther away with different material properties. This segmentation allows each layer to be optimized for its specific function, reducing overall parasitic capacitance while maintaining manufacturability through a structured, modular approach.
3Length of moving object
If insulating films with varying materials and structures are implemented to reduce parasitic capacitance, then the line interval can be narrowed, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs a preliminary action approach by forming the insulating films in a specific sequence during the manufacturing process. The first insulating film is formed closer to the via contact before the second insulating film is formed farther away. This predetermined sequencing of manufacturing steps, combined with the specific material selection and thickness control, enables the complex multi-layer insulating structure to be manufactured systematically, reducing process complexity despite the multiple layers involved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enabling narrower line intervals and improved downscaling of the array chip, enhancing performance and scalability of semiconductor storage devices.
Implementation Method 1
there is a risk of an increase in the parasitic capacitance between the lines and the parasitic capacitance between lines and via contacts
Implementation Method 2
A plurality of second insulating films 25b are located correspondingly on the bit lines 23, respectively
Data Source
AI summary
A device includes first-lines located in a first direction of a first insulator. The first lines are arrayed in a second direction and extend in a third direction. Second insulators are located on the first-lines, respectively. The width of each of the second insulators in the second direction in a face in contact with a corresponding first-line is smaller than the width of the corresponding first-line. Third insulators are located correspondingly on the first-lines, respectively, and each coat both side surfaces of an associated one of the second insulators. A fourth insulator is located on the third insulators. A fifth insulator is located on the fourth insulator. A first contact penetrates through the second to fifth insulators to be connected to the first-lines. A second line is located on the first contact. The first contact, or the second and fourth insulators are located in the first direction of the first-lines.