Bit Line Void Sealing Structure for Low-Capacitance DRAM Scaling
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Solution Overview
Problem
The reduction in feature size of semiconductor integrated circuits leads to increased parasitic capacitance between adjacent conductors due to thinner dielectric layers, compromising structural stability and integrity.
Innovation Solution
A manufacturing method involving the formation of spacers with varying heights to create voids and sealing layers, ensuring precise thickness and support, thereby enhancing structural stability and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the dielectric layer thickness is reduced to accommodate smaller feature sizes, then the integration density is improved, but the parasitic capacitance between adjacent conductors increases and structural stability deteriorates
Solution Approach 1:
The patent divides the spacer structure into multiple segments with different heights (first spacer, second spacer, third spacer). Each spacer segment serves a specific function: the first spacer provides initial support, the second spacer creates the void space, and the third spacer provides additional support. This segmentation allows the structure to maintain stability while accommodating the thin dielectric layer required for high integration density.
Solution Approach 2:
The patent applies local quality by creating a non-uniform spacer structure where different regions have different heights and properties. The spacers are positioned at specific locations (first, second, and third spacers at different heights) to provide localized support where needed. This allows the dielectric layer to be thin in most areas for high density while maintaining structural integrity at critical locations through the multi-level spacer support system.
2Area of moving object
If the dielectric layer thickness is reduced to accommodate smaller feature sizes, then the integration density is improved, but the structural stability deteriorates
Solution Approach 1:
The spacer structure is segmented into multiple levels with different heights. The first spacer provides baseline support, the second spacer creates the necessary void space for capacitor formation, and the third spacer provides additional support. This segmentation distributes the structural support function across multiple elements, enhancing overall stability despite the reduced dielectric thickness.
Solution Approach 2:
The patent employs beforehand cushioning by pre-forming the multi-level spacer structure before subsequent processing steps. The spacers are created in advance to provide structural cushioning and support, preventing collapse or deformation of the thin dielectric layer during later manufacturing processes. The void space created by the second spacer acts as a cushioning region that maintains structural integrity.
3Stability of the object's composition
If multiple spacers with varying heights are formed to create voids and sealing layers, then the structural stability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a nested doll structure where spacers are positioned within and around each other in a hierarchical arrangement. The first spacer is positioned at a lower level, the second spacer creates a void space above it, and the third spacer provides support at an even higher level. This nested arrangement efficiently uses vertical space and provides multi-level support while maintaining a relatively compact structure, reducing the complexity increase that would otherwise result from multiple separate support elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures high structural stability and low parasitic capacitance by defining sealing layer thickness through multiple spacers, preventing collapse and maintaining efficient signal transmission.
Implementation Method 1
forming a first sealing film by a deposition process, the first sealing film covers the top surface of the first spacer and plugs a top opening of the void
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: providing a substrate and a bit line structure located on the substrate, the bit line structure including a top dielectric layer and capacitive contact holes being provided on two opposite sides of the bit line structure; forming a first spacer covering a sidewall of the top dielectric layer between the bit line structure and the capacitive contact hole and a second spacer covering a sidewall of the first spacer, a top surface of the second spacer being higher than that of the first spacer; removing at least part of the top dielectric layer to form a first void; forming a first sealing film by a deposition process; and removing a part of the first sealing film which is higher than the top surface of the second spacer, the remaining first sealing film is a first sealing layer.