Bit Line Voltage Adjustment for 3D NAND Read Power Reduction
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in accurately sensing the threshold voltage of memory cells while minimizing power consumption, particularly in 3D NAND stacked memory structures.
Innovation Solution
The implementation of a memory apparatus and method that adjusts bit line voltage based on the amount of programmed memory cells in blocks, using temperature and distance compensation to determine the threshold voltage during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bit line voltage is adjusted based on programmed memory cell amount, then threshold voltage sensing accuracy is improved, but device complexity increases
Solution Approach 1:
The bit line voltage is made dynamic rather than fixed, adjusting automatically based on the programmed state of memory cells. The control means determines the amount of programmed cells and adjusts the bit line voltage accordingly, allowing the system to adapt to different operational conditions and optimize sensing accuracy for each state.
Solution Approach 2:
The patent changes the voltage parameter of the bit line based on the programmed memory cell amount. By varying the bit line voltage parameter according to the operational state (amount of programmed cells), the system achieves accurate threshold voltage sensing across different data states without requiring complex additional hardware.
2Measurement precision
If bit line voltage temperature compensation is applied, then sensing accuracy is improved, but power consumption increases
Solution Approach 1:
The bit line voltage incorporates dynamic temperature compensation that adjusts automatically based on temperature conditions. The control means monitors temperature and adjusts the bit line voltage accordingly, enabling accurate sensing across temperature variations without requiring excessive power consumption through passive thermal compensation mechanisms.
Solution Approach 2:
The patent applies temperature compensation by changing the bit line voltage parameter in response to temperature variations. This allows the sensing system to maintain accuracy across different temperature conditions by adjusting the voltage parameter to compensate for thermal effects on threshold voltage measurements.
3Device complexity
If fixed bit line voltage is used, then device complexity is reduced, but sensing accuracy deteriorates
Solution Approach 1:
The system transitions from a static fixed voltage approach to a dynamic adaptive voltage approach. The control means automatically adjusts the bit line voltage based on real-time conditions (programmed cell amount and temperature), enabling accurate sensing across diverse operational states while maintaining relatively simple device architecture.
Solution Approach 2:
Instead of using a fixed voltage parameter, the patent implements a variable voltage parameter that changes based on operational conditions. This allows the bit line voltage to be optimized for each sensing operation according to the programmed state and temperature, significantly improving sensing accuracy without requiring complex additional hardware components.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.