Bit Line Voltage Adjustment for Non-Volatile Memory Arrays
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Solution Overview
Problem
In non-volatile semiconductor memory, applying uniform voltages to all memory cells during read operations leads to inefficiencies due to line resistance, resulting in increased power consumption and reduced performance, as cells farther from the voltage source require higher voltages to compensate for voltage drop.
Innovation Solution
Implementing a system where bit line voltages are adjusted based on the distance of memory cells from the voltage source, allowing cells that need higher voltages to receive them while those that don't require lower voltages, thereby optimizing voltage application across the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform voltage is applied to all memory cells, then all cells receive sufficient voltage to operate, but power consumption increases and cells closer to the voltage source experience unnecessary voltage stress
Solution Approach 1:
The patent applies different voltage levels to different groups of bit lines based on their distance from the voltage source. Specifically, bit lines connected to memory cells farther from the voltage source receive higher voltages to compensate for voltage drop, while bit lines connected to closer cells receive lower voltages. This local differentiation resolves the contradiction by ensuring reliable operation where needed while reducing unnecessary power consumption and voltage stress in other areas.
2Reliability
If higher voltage is applied to compensate for line resistance, then memory cells farther from the voltage source can be read, but power consumption increases
Solution Approach 1:
The invention implements local quality by segmenting bit lines into multiple groups and applying different voltage levels to each group based on their specific distance from the voltage source. This ensures that only the bit lines requiring higher voltage to overcome line resistance actually receive it, while others receive appropriate lower voltages, thereby maintaining reliable voltage delivery to distant cells without unnecessary energy loss across the entire system.
3Device complexity
If same voltage is used for all bit lines, then circuit design is simplified, but performance is reduced due to unnecessary voltage application to close cells
Solution Approach 1:
The patent applies local quality by creating multiple voltage groups for bit lines based on their distance characteristics. This segmentation allows the system to optimize read operation speed by applying appropriate voltage levels to each group, improving overall productivity while the voltage control circuit manages the complexity through systematic grouping rather than individual control of each bit line.
Solution Approach 2:
The invention segments the bit lines into multiple groups (e.g., first group, second group, third group) with different voltage characteristics. This segmentation enables differentiated voltage application, improving read performance by ensuring each group receives the appropriate voltage level, while the systematic grouping approach keeps the control circuit complexity manageable through pattern-based control.
Data Source
AI summary
An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.