Bit Line Voltage Clamping for Flash Memory Read Noise Reduction
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Solution Overview
Problem
In high-density flash memory implementations, coupling noise between bit lines and data lines during read operations is a significant issue due to capacitance between closely placed conductive structures, leading to potential sensing errors and reduced reliability.
Innovation Solution
The method involves precharging bit lines to a first level (VPRE) and controlling current flow through selected memory cells to prevent voltage changes from exceeding a range between VPRE and a second level (VKEEP), which is lower than VPRE and higher than the reference voltage, thereby reducing coupling noise and ensuring accurate data sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If bit lines and data lines are placed closely together to save layout area, then device density is improved, but coupling noise between lines increases
Solution Approach 1:
The bit lines are precharged to a first voltage level (VPRE) before the read operation begins. This preliminary action establishes a known initial state for all bit lines, ensuring that any subsequent voltage changes during reading are due solely to the memory cell states and not from uneven initial conditions or coupling noise effects.
Solution Approach 2:
The patent introduces a clamping mechanism that limits the voltage swing of bit lines to a specific range between VPRE and VKEEP during read operations. By constraining the voltage parameter within this controlled range, the patent reduces the coupling noise generated by voltage transitions on closely spaced bit lines, thereby mitigating the harmful effect while maintaining high density.
2Measurement precision
If current flow is enabled through selected memory cells to read data, then data sensing is achieved, but voltage changes on bit lines cause coupling noise
Solution Approach 1:
The patent applies a clamping mechanism that dynamically adjusts the voltage parameter of bit lines during read operations. The clamp circuit ensures that bit line voltage remains within the controlled range [VPRE, VKEEP], preventing excessive voltage swings that would generate coupling noise while still allowing sufficient current flow through selected memory cells for accurate data sensing.
Solution Approach 2:
The clamping circuit operates as a feedback mechanism that continuously monitors bit line voltage and adjusts the current flow through the memory cells accordingly. When the voltage approaches the upper or lower limits of the acceptable range, the clamp circuit automatically reduces or blocks current flow to maintain voltage within the desired range, thereby reducing coupling noise while preserving sensing accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes coupling noise on bit lines and data lines, enhancing the reliability of read operations by limiting the maximum voltage swing and reducing the risk of sensing errors, thus improving the overall performance of flash memory devices.
Implementation Method 1
There is capacitance between closely placed bit lines, between closely placed data lines, and in conductive structures surrounding the bit lines and the data lines
Implementation Method 2
Reading operations on memory cells in a NAND flash memory includes charging and discharging the capacitance associated with the bit lines and data lines coupled to the memory cells using electrical current through the memory cells
Data Source
AI summary
A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level VKEEP, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.