Bit Line Voltage Control in 3D NAND Memory
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Solution Overview
Problem
In three-dimensional NAND memory devices, existing bit line voltage control methods lead to undesirable coupling and errors during programming operations due to non-uniform voltage biases, which affect the accuracy and reliability of memory cell programming.
Innovation Solution
A multi-stage voltage ramping sequence is applied to bit line terminals, where a first voltage is applied to one bit line while maintaining another at ground, followed by multiple stages of voltage increases to nominal levels, maintaining a constant voltage differential to reduce coupling and improve uniformity, and the bit line terminals are left floating during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit line voltage control methods are used, then the programming operation can be performed, but undesirable coupling and errors occur due to non-uniform voltage biases
Solution Approach 1:
The voltage ramping process is divided into multiple discrete stages (first stage, second stage, third stage, etc.), where each stage applies a specific voltage differential to achieve progressive voltage uniformity across bit line terminals. This segmentation allows precise control over voltage distribution to eliminate coupling effects.
Solution Approach 2:
Before the actual programming operation, preliminary voltage ramping stages are performed to establish uniform voltage biases across all bit line terminals. This preliminary action ensures that when programming begins, the bit lines are already in a uniform state that prevents coupling and errors.
2Manufacturing precision
If multi-stage voltage ramping is applied to achieve uniform voltage biases, then programming accuracy improves, but the control process becomes more complex
Solution Approach 1:
The invention systematically changes voltage parameters (voltage levels, voltage differentials, ramping rates) across multiple stages to achieve uniform bit line voltages. Each stage uses specific parameter values that are optimized to progressively eliminate voltage non-uniformity while maintaining manageable control complexity.
3Object-generated harmful factors
If bit line terminals are left floating during programming, then coupling side effects are reduced, but voltage control becomes more difficult
Solution Approach 1:
The bit line terminal state is made dynamic rather than static - transitioning from grounded state during voltage ramping to floating state during programming, and back to grounded state afterward. This dynamic state change allows the system to reduce coupling effects during programming while maintaining voltage control during other phases.
Data Source
AI summary
The present disclosure provides a method for controlling bit line voltages in a three-dimensional memory device. The method includes ramping up a bit line clamp regulation voltage and a control signal regulation voltage. The method also includes ramping up a bit line clamp enabling voltage and a control signal enabling voltage. The method also includes increasing a bit line clamp voltage in one stage, and increasing a control signal voltage in two stages. The method also includes decreasing the control signal voltage. The method also includes ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage. The method further includes decreasing the bit line clamp voltage.