Low Couple Effect Bit-Line Voltage Generator Circuit
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Solution Overview
Problem
Conventional bit-line voltage generators in memory circuits suffer from long discharge times and unstable voltage due to excessive coupling effects, leading to parasitic capacitor over-discharge and voltage overshoot.
Innovation Solution
A low couple effect bit-line voltage generator is designed with a discharge enhanced bias source and a switch unit, incorporating a clamp transistor, a switch transistor, a leakage resistor, and a hold capacitor to reduce coupling effects and stabilize the bias voltage applied to the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the conventional voltage regulator uses only resistors for discharging the parasitic capacitor, then the circuit structure is simple, but the discharge time is very long and the voltage becomes unstable
Solution Approach 1:
The bias source transitions from a static resistor-only discharge path to a dynamic configuration that can switch between high-impedance (resistors only) and low-impedance (transistor-assisted) discharge modes, enabling rapid discharge when needed while maintaining simplicity at other times
Solution Approach 2:
The discharge path impedance is dynamically changed by activating the third transistor to create a low-impedance path, significantly reducing discharge time from conventional long durations to a rapid timescale without requiring a completely different circuit architecture
2Device complexity
If the parasitic capacitor discharges through resistors only, then the circuit is simple, but the settling time is excessively long causing over-discharge and voltage instability
Solution Approach 1:
The third transistor is pre-configured in the bias source circuit to provide an immediate low-impedance discharge path when the switch transistor turns on, eliminating the delay associated with capacitor charging and preventing over-discharge before the voltage regulator can respond
Solution Approach 2:
The voltage regulator monitors the bit-line voltage and provides feedback control, working in conjunction with the enhanced discharge path to quickly restore stability after the transient disturbance caused by parasitic capacitor discharge
3Speed
If the switch transistor is turned on rapidly, then the voltage rises quickly, but the parasitic capacitor discharges excessively causing voltage overshoot and instability
Solution Approach 1:
The third transistor provides a preliminary discharge path that counteracts the excessive charging effect before it can cause significant overshoot, balancing the rapid voltage rise by simultaneously enabling controlled parasitic capacitor discharge
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces coupling effects and enhances discharge capability, resulting in a stable and rapid recovery of voltage, eliminating overshoot and ensuring a stable bias voltage for the memory array.
Implementation Method 1
A parasitic capacitor Cp exists between the gate and the source of the clamp transistor Mclamp
Data Source
AI summary
A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.