Bit Line Voltage Setup Using Step Pulse and Ramp Signal
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently setting up bit line voltages during program operations, leading to current peaks and potential reliability issues due to rapid charge inflow, which existing technologies struggle to manage effectively.
Innovation Solution
A semiconductor memory device and method that utilize a bit line setup control unit to apply a step pulse followed by a ramp signal to the gate electrode of a transistor in the page buffer, controlling the bit line voltage setup to prevent current peaks without increasing program time, by using a control circuit that includes a reference voltage amplification unit, ramp signal generation unit, and ramp signal activation unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a rapid voltage setup is applied to the bit line during program operation, then the program speed is improved, but current peaks occur causing reliability issues
Solution Approach 1:
The patent applies a dynamic control signal with two distinct phases: an initial step pulse that rapidly changes voltage to enable fast programming, followed by a ramp signal that gradually increases voltage to maintain stability. This dynamic transition from rapid change to gradual adjustment resolves the contradiction between speed and reliability by adapting the voltage setup rate to different operational stages.
Solution Approach 2:
The control signal is structured as a periodic sequence consisting of a step pulse phase followed by a ramp signal phase. This periodic action pattern allows the system to repeatedly execute the fast setup followed by stable maintenance, achieving both high program speed and sustained reliability through cyclical application of different voltage rates.
2Speed
If a step pulse is applied to the gate electrode, then the voltage setup speed is improved, but current peaks are generated
Solution Approach 1:
The step pulse is applied as a preliminary action to rapidly establish the initial voltage condition on the bit line, achieving fast setup. This is immediately followed by the ramp signal that serves as a corrective action to gradually adjust the voltage and eliminate current peaks, thus resolving the harmful effect while preserving the speed benefit.
Solution Approach 2:
The patent converts the harmful current peaks generated by the step pulse into a beneficial two-stage process: the step pulse provides rapid voltage establishment (the benefit), while the subsequent ramp signal manages the current peaks (the harm). By accepting and managing the harmful effect rather than avoiding it, the system achieves both speed and reliability.
3Reliability
If a ramp signal alone is used for bit line voltage setup, then current peaks are suppressed, but program time increases
Solution Approach 1:
The voltage setup process is segmented into two distinct phases: a step pulse phase for rapid initial voltage establishment and a ramp signal phase for gradual voltage adjustment. This segmentation allows each phase to optimize for its specific function - speed in the first phase and current suppression in the second - thereby resolving the contradiction between reliability and time.
Solution Approach 2:
The patent changes the voltage setup parameter dynamically by transitioning from a fixed ramp signal to a composite signal comprising both step pulse and ramp components. This parameter change enables the system to achieve both fast setup (through the step pulse) and current peak suppression (through the ramp signal), eliminating the trade-off between reliability and program time.
Data Source
AI summary
Provided herein may be a control circuit, peripheral circuit, semiconductor memory device and methods of operating the device and circuits. The method of operating a semiconductor memory device may include applying a control signal having a form, in which a step pulse is combined with a ramp signal, to a gate electrode of a transistor for setting up a voltage of a bit line of the selected memory cell. The method of operating a semiconductor memory device may include applying a program pulse to a word line of the selected memory cell.