Bit Line Voltage Step-Up for Non-Volatile Memory Programming
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in accurately programming threshold voltage ranges while reducing programming time, especially as memory devices are scaled down, leading to issues with narrow threshold voltage distributions and increased programming noise.
Innovation Solution
A programming technique that involves stepping up the bit line voltage for storage elements close to completing their target data state, using a range of program pulses for each target data state, and optimizing the gap between verify levels to ensure a majority of storage elements are slowed down, resulting in a narrower threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled down to increase storage capacity, then storage density is improved, but threshold voltage distribution becomes narrower and programming noise increases
Solution Approach 1:
The patent applies dynamics by making the bit line voltage adjustable and time-dependent during the programming process. The voltage is dynamically changed from an initial level to a final level based on the programming progress, allowing the system to adapt to the changing threshold voltage distribution characteristics as memory devices are scaled down.
Solution Approach 2:
The patent changes the bit line voltage parameter during programming to optimize threshold voltage distribution. By adjusting the voltage levels and timing, the system compensates for the narrower threshold voltage distribution and increased programming noise inherent in scaled-down memory devices, thereby improving manufacturing precision.
2Productivity
If programming speed is increased to reduce programming time, then productivity is improved, but threshold voltage distribution becomes wider and accuracy decreases
Solution Approach 1:
The patent employs periodic action by using multiple programming pulses with different bit line voltage levels. The programming process is divided into stages with verify operations in between, creating a periodic pattern of programming-verify cycles that allow speed optimization without sacrificing accuracy.
Solution Approach 2:
The system dynamically adjusts the bit line voltage based on the programming progress and verify results. By making the voltage adjustable rather than fixed, the system can optimize programming speed while maintaining threshold voltage distribution accuracy, resolving the contradiction between productivity and manufacturing precision.
3Loss of time
If bit line voltage is increased to speed up programming, then programming time is reduced, but threshold voltage distribution widens due to excessive programming noise
Solution Approach 1:
The patent makes the bit line voltage dynamic by adjusting it from an initial level to a final level during programming. This dynamic adjustment allows the system to speed up programming when appropriate while preventing excessive voltage that would widen threshold voltage distribution, thereby reducing programming time without sacrificing manufacturing precision.
Solution Approach 2:
The system changes the bit line voltage parameter during the programming process based on observed threshold voltage distribution characteristics. By monitoring and adjusting the voltage level, the system optimizes the balance between programming speed and threshold voltage distribution width, resolving the contradiction between time loss and manufacturing precision.
Data Source
AI summary
Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.