Bit lines with air gaps and low-k dielectric for reduced parasitics
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Solution Overview
Problem
The increasing demand for smaller and denser semiconductor devices leads to higher parasitic resistances and capacitances in bit lines, degrading device performance, particularly in memory devices, due to narrower traces and closer spacing, which results in increased parasitic resistances and capacitances, affecting signal switching speed and the likelihood of failed read operations.
Innovation Solution
The method involves forming bit lines with a first electrically conductive material for mechanical strength, creating air gaps between them, reinforcing these gaps with a low-k dielectric material, and replacing parts of the first conductive material with a more conductive second material, such as copper, to achieve low parasitic resistances and capacitances while maintaining mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are made narrower and spaced closer together to reduce chip area, then device density is improved, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent changes the material parameter of bit lines from conventional materials (copper, aluminum, tungsten) to conductive polymers, which have different electrical and mechanical properties. This material substitution allows achieving lower parasitic resistance and capacitance while maintaining the narrow, closely-spaced configuration needed for high device density.
Solution Approach 2:
The patent employs composite structures combining conductive polymer materials with other materials to create bit lines that simultaneously achieve low parasitic resistance, low parasitic capacitance, and sufficient mechanical strength. The composite approach allows optimizing multiple properties that cannot be independently optimized with single materials.
2Reliability
If conventional conductive materials (copper, aluminum, tungsten) are used, then electrical conductivity is achieved, but mechanical strength is insufficient when traces are narrow
Solution Approach 1:
The patent uses composite material structures where conductive polymers are combined with other materials to provide both electrical conductivity and mechanical strength. The conductive polymer layer provides the necessary electrical properties, while the composite structure or underlying/overlying layers provide mechanical reinforcement to prevent breakage in narrow traces.
Solution Approach 2:
The patent changes the material composition from conventional metals to conductive polymers, fundamentally altering the material parameters to achieve a balance between electrical conductivity and mechanical properties that is suitable for narrow, closely-spaced bit lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in bit lines with reduced parasitic resistances and capacitances, enhancing the performance of semiconductor devices by improving signal switching speed and reducing the likelihood of failed read operations, while maintaining mechanical integrity.
Implementation Method 1
air gaps between the bit lines
Implementation Method 2
reinforcing these gaps with a low-k dielectric material
Implementation Method 3
replacing parts of the first conductive material with a more conductive second material
Data Source
AI summary
Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches. The method also includes recessing the first electrically conductive material and replacing removed portions of the first electrically conductive material with a second electrically conductive material.