Bit-Mapped Index for Fast Network Address Lookup
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Solution Overview
Problem
Network devices face memory and processor-intensive challenges in identifying next-hop addresses for data packets, which can be improved with specialized hardware but require efficient data structure organization and processing methods.
Innovation Solution
A network device employs a bit-mapped index into an address table with organized data structures, including a Result Table and Range Table, to rapidly identify packet processing instructions by parsing address prefixes and using Boolean values to locate intermediary values and instruction parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional routing tables are used for address lookup, then comprehensive routing information can be stored, but memory access time increases and processing speed decreases
Solution Approach 1:
The routing table is segmented into two separate data structures: a first data structure storing address prefixes and instruction parameters, and a second data structure storing detailed address-to-next-hop mappings. This segmentation allows the system to first quickly identify the relevant address range using the first data structure, then access only the necessary portion of the second data structure, thereby reducing overall memory access time and improving lookup speed.
Solution Approach 2:
The patent introduces a hierarchical dimension to the traditional flat routing table structure. By organizing data in multiple levels (first data structure for range identification, second data structure for specific mappings), the system transforms a single-dimension linear search problem into a multi-dimensional hierarchical lookup, enabling faster identification of relevant data ranges and reducing the search space in subsequent steps.
2Productivity
If specialized hardware is used for packet processing, then processing speed improves, but device complexity and cost increase
Solution Approach 1:
The patent replaces the need for specialized hardware mechanisms with an optimized software-based data structure organization. By structuring the routing information in a hierarchical manner with indexed ranges and intermediary values, the system achieves high-speed packet processing using general-purpose processors, eliminating the need for complex dedicated hardware while maintaining high productivity.
3Reliability
If detailed address information is stored in a single structure, then complete routing data is available, but memory usage and access overhead increase
Solution Approach 1:
The patent extracts and separates different types of routing information into distinct data structures. The first data structure contains address prefix ranges and instruction parameters, while the second data structure contains specific address-to-next-hop mappings. This extraction allows the system to access only the necessary portion of routing information for each lookup, reducing memory access energy while maintaining complete and accurate routing data availability.
Data Source
AI summary
Aspects and implementations of the present disclosure are directed to a network device. The network device includes memory for storing a first dataset comprising first data structures, a second dataset comprising second data structures, and a set of Boolean values. Each first data structure includes an address and a corresponding instruction parameter. Each second data structure includes an address prefix and at least one intermediary value. Each Boolean value corresponds to a respective address prefix and indicates whether the second dataset includes a second data structure with the respective address prefix. The network device is configured to identify a first address and a first address prefix for a first data packet, identify one or more intermediary values for the first address prefix using the set of Boolean values, and identify a packet processing instruction parameter using the one or more identified intermediary values.