Bit Matrix Multiplication Unit Register Reorganization

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Solution Overview

Problem

Bit matrix multiplication units face inefficiencies when reorganizing data from multiple matrices, requiring multiple register transfers and instruction cycles in conventional architectures.

Innovation Solution

A processor with a bit matrix multiplication unit that allows explicit identification and manipulation of double precision registers for matrix multiplication, enabling efficient reorganization of data through specific instructions like sbmm and sbmmt, which reduce the number of instruction cycles needed for mixing data from multiple packets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional BMM unit is used for reorganizing data from multiple matrices, then data reorganization capability is provided, but processing efficiency deteriorates due to multiple register transfers and instruction cycles

Engineering Contradiction:

Improvedata reorganization capabilityVSAvoidprocessing efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges multiple single-precision registers into double-precision registers, allowing two 32-bit registers to be jointly addressed as a single 64-bit register. This combining of register resources enables the BMM unit to process data from multiple matrices more efficiently by reducing the number of separate register transfer operations needed, thereby improving processing efficiency while maintaining data reorganization capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The double-precision register file provides multi-functionality by serving both as individual single-precision registers and as combined double-precision registers. This universal register structure allows the same hardware resource to handle different data organization requirements, enabling efficient processing of multiple matrices without requiring additional dedicated registers for each operation

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Loss of time

If explicit double precision register identification is implemented, then instruction cycle reduction is achieved, but register file complexity increases

Engineering Contradiction:

Improveinstruction cycle countVSAvoidregister file structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The register file is segmented into pairs of single-precision registers that can be jointly addressed as double-precision registers. Each double-precision register consists of two single-precision registers (e.g., even and odd numbered registers), allowing the system to reduce instruction cycles by treating them as a unified 64-bit entity while maintaining the underlying single-precision structure for flexibility

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9898251B2Bit-matrix multiplication using explicit register

Publication Date: 2018.02.20 KALRAY

AI summary

The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.