Bit-Pair Memory Deinterleaver for Multi-Stage Wireless Interleaving
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Solution Overview
Problem
Existing deinterleavers for advanced interleaving schemes in wireless communication systems are costly in terms of silicon area and not scalable, particularly for multi-stage interleaving schemes like the three-stage interleaving used in MultiBand OFDM Physical Layer Specification.
Innovation Solution
A deinterleaver design that preprocesses data bits into pairs, stores them in memory, and uses a read/write address generator to efficiently manage memory addresses, allowing for simultaneous symbol and bit deinterleaving, with a control mechanism to adapt to different data rates and interleaving schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If direct mapping of deinterleavers for advanced interleaving schemes is used, then the deinterleaver can handle multi-stage interleaving, but silicon area increases and power consumption increases
Solution Approach 1:
The deinterleaver is divided into multiple functional units: a symbol deinterleaver unit for reversing symbol interleaving, a tone deinterleaver unit for reversing tone interleaving, and a cyclic shift unit for reversing cyclic shifts. Each unit handles a specific stage of the interleaving process, allowing the system to manage complex multi-stage interleaving through modular, manageable components that reduce overall silicon area requirements.
Solution Approach 2:
The patent implements a nested structure where the symbol deinterleaver, tone deinterleaver, and cyclic shift unit are hierarchically organized. The symbol deinterleaver operates on the outer layer, the tone deinterleaver on the middle layer, and the cyclic shift unit on the inner layer. This nesting allows the deinterleaver to process multiple interleaving stages within a compact, integrated architecture, reducing the total silicon area compared to separate independent units.
2Adaptability or versatility
If direct mapping of deinterleavers for advanced interleving schemes is used, then the deinterleaver can handle multi-stage interleaving, but power consumption increases
Solution Approach 1:
By segmenting the deinterleaver into specialized units (symbol deinterleaver, tone deinterleaver, cyclic shift unit), each unit can be optimized for its specific function with minimal power consumption. The segmentation allows the system to activate only the necessary units for each deinterleaving operation, avoiding the continuous power consumption that would result from a monolithic design handling all interleaving types.
Solution Approach 2:
The patent employs dynamic control mechanisms where the deinterleaver units are activated based on the specific interleaving scheme being used. The system can adaptively enable or disable certain units depending on whether symbol interleaving, tone interleaving, or cyclic shifts are present, thereby reducing power consumption by avoiding unnecessary processing operations while maintaining full adaptability to different interleaving configurations.
3Ease of manufacture
If conventional deinterleaver design is used, then implementation is straightforward, but complexity increases and scalability decreases
Solution Approach 1:
The deinterleaver is segmented into distinct functional units, each responsible for a specific deinterleaving operation. This segmentation simplifies the design and implementation of each individual unit, as they can be developed and tested independently. The modular structure also improves scalability, as new units can be added or existing units modified without affecting the entire system, thereby reducing overall complexity while maintaining ease of manufacture.
Solution Approach 2:
The patent creates a universal deinterleaver architecture where the same basic structure can handle multiple interleaving schemes through configurable units. The symbol deinterleaver, tone deinterleaver, and cyclic shift unit can be selectively activated based on the required functionality, making the system universally applicable to different communication standards and interleaving configurations without increasing complexity.
4Ease of manufacture
If conventional deinterleaver design is used, then implementation is straightforward, but scalability decreases
Solution Approach 1:
The segmented architecture allows the deinterleaver to be scaled by adding or removing specific functional units based on the requirements of different communication systems. Each unit is self-contained and can be independently configured, enabling the system to scale from simple to complex interleaving schemes without redesigning the entire architecture, thereby maintaining ease of manufacture while improving scalability and adaptability.
Solution Approach 2:
The nested structure provides a hierarchical framework where core deinterleaving functions are contained within larger, more complex deinterleaving capabilities. This nesting allows the system to maintain a simple, straightforward implementation for basic functions while providing scalability to handle advanced multi-stage interleaving schemes by simply activating additional nested layers, thus preserving ease of manufacture while enhancing adaptability.
Data Source
AI summary
A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.