Bit-Pattern Testing of High-Resolution Digital Counters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for testing high-resolution counters in safety-critical systems, such as Software Watchdog Timers, are time-intensive and unsuitable for ensuring boot times within the required 50 milliseconds, especially for counters with more than 16 bits.
Innovation Solution
A method involving a software module that tests the functionality of digital hardware counters by setting specific bit patterns and monitoring bit flips during counting operations, allowing for efficient testing of counters with 16, 32, or 64 bits without prolonged time consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional waiting methods are used to test counter functionality by allowing the counter to reach its final value, then the counter testing is thorough and reliable, but the testing time becomes excessively long for high-resolution counters
Solution Approach 1:
The software module performs preliminary actions by setting the count value to specific test patterns (such as all ones or all zeros) before starting the counter. This allows the test to begin from a known state and verify counter operation without waiting for the counter to naturally reach its final value, significantly reducing testing time while maintaining reliability
Solution Approach 2:
The invention changes the parameters being tested from the full count value to individual bit patterns. By setting specific bit patterns (all ones, all zeros, alternating patterns) and verifying the counter responds correctly to these specific parameter configurations, the test achieves comprehensive coverage without requiring the counter to complete a full counting cycle, thus reducing testing time
2Measurement precision
If the counter resolution is increased to provide higher precision timing, then the timing precision is improved, but the traditional testing methods become even more time-consuming
Solution Approach 1:
The testing approach is segmented into independent bit-pattern tests rather than a single continuous wait-for-final-value test. The software module tests different bit patterns (MSB patterns, LSB patterns, alternating patterns) separately and efficiently, allowing high-resolution counters to be tested without the testing time increasing proportionally with the counter resolution
Solution Approach 2:
The invention changes the testing parameters to focus on bit-level patterns rather than waiting for full counter resolution to manifest. By using patterns like all ones (11...1), all zeros (00...0), and alternating patterns (1010...), the test verifies counter functionality at the bit level without requiring the counter to count through all possible values, thus maintaining timing precision while reducing test time
Data Source
Figure 1~2
Figure 3~4
Figure 5a~5d
AI summary
Solutions for testing a digital hardware counter circuit (108) are disclosed. A software module (1022) executed by a microprocessor (102) is configured to test a plurality of most significant bits of a count value (CNT) of a counter (1080) of the counter circuit (108) by repeating a sequence of steps for each bit position (N) of the plurality of most significant bits of the count value (CNT). Specifically, the software module (1022) sets (5004) the count value (CNT) to a binary value (T). In case of a down counter (1080), the bit of the binary value (T) at the current bit position (N) is set to high and the lower bits of the binary value (T) are set to low. Conversely, in case of an up counter (1080), the bit of the binary value (T) at the current bit position (N) is set to low and the lower bits of the binary value (T) are set to high. Next, the software module (1022) enables (5006) the counter (1080), whereby the counter (1080) varies the count value (CNT). After a given time-period, the software module disables (5008) the counter (1080) and determines (5010) whether one or more bits of the count value (CNT) have a respective expected value. When at least one of the one or more bits of the count value (CNT) does not have the respective expected value, the software module (1022) signals (5020) a malfunction of the digital hardware counter circuit (108). Otherwise, the software module (1022) selects a next bit position (N) of the plurality of most significant bits of the count value (CNT).