Bit Permutation Circuitry Using Multi-Level Shifter Network
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Solution Overview
Problem
Existing bit permute units in data processing systems are large and complex, leading to increased cost, power consumption, and complexity, while attempts to reduce size result in deeper logic and higher latency.
Innovation Solution
An apparatus with an interface for receiving input and control operands, utilizing bit permute circuitry to treat data as fixed-size portions, and a multi-level network of shifter circuits to perform bit permutation operations efficiently, with control circuitry generating control signals to manage shift operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large and complex circuitry is provided to deeply inspect and perform computations on control data, then the speed of operation is improved, but the area and cost of the bit permute unit increase significantly
Solution Approach 1:
The patent segments the bit permute operation into two distinct phases: a setup phase that computes a compressed representation of the control data, and an execution phase that uses this compressed form to drive a multi-level network of multiplexers. This segmentation eliminates the need for deeply inspecting the full control data during the critical path of the permutation operation, thereby improving speed while reducing the area required for control logic circuitry.
Solution Approach 2:
The patent introduces an intermediate compressed representation of the control data that serves as a mediator between the control operand and the permutation operation. This compressed form captures the essential permutation information in a compact format, allowing the execution phase to operate efficiently with reduced logic depth and smaller area, while still achieving the desired permutation effect.
2Area of stationary object
If the size and complexity of the bit permute unit are reduced, then area and cost are improved, but the logic depth increases requiring multiple execute cycles
Solution Approach 1:
The patent performs preliminary computation of the control data compression during the setup phase, before the actual permutation operation needs to execute. This preliminary action prepares the compressed control representation in advance, so that the execution phase can proceed with shallow logic depth in a single cycle, avoiding the need for multiple execute cycles and thereby reducing latency.
3Productivity
If dedicated bit permute units are arranged to handle vectors of data elements, then throughput is improved, but the area and complexity of the system increase
Solution Approach 1:
The patent designs a universal bit permute unit that can handle vectors of data elements of various sizes and configurations using the same compressed control representation mechanism. The multi-level network of multiplexers is configured to process multiple data elements simultaneously, with the compressed control form providing the necessary routing information for all elements. This universality allows high throughput across different data element sizes without proportionally increasing the complexity of the control logic, as the same compression and execution framework applies regardless of vector configuration.
Data Source
AI summary
An apparatus and method are provided for performing bit permutation operations. The apparatus has an interface for receiving an input data operand and a control operand. The input data operand comprises one or more data elements, each data element comprising a plurality of bits, and the control operand provides control information identifying bit permutations required when performing a given bit permutation operation on each data element. The bit permute circuitry treats the input data operand as a plurality of fixed size data portions, each data element comprising one or more of the data portions with the number being dependent on the data element size. The bit permute circuitry performs bit permutation operations on each data portion of the input data operand, using the control information provided for that data portion, generating, for each data portion, at least one intermediate result. Result generation circuitry generates, from the intermediate results, a final result operand comprising one or more result elements, each result element providing the result of performing the given bit permutation operation on the corresponding data element of the input data operand. The result generation circuitry comprises a multi-level network of shifter circuits, shifter circuits at a first level performing shift operations using as inputs at least a subset of the intermediate results, and shifter circuits at each subsequent level performing shift operations using inputs derived from the outputs of the shifter circuits at a preceding level of the network. Control circuitry analyses the control information provided by the control operand in order to generate control signals that control the shift operations performed by the shifter circuits.