Bit-Pipelined Rank Filter for Scalable Median Extraction

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Solution Overview

Problem

Conventional rank filters are not scalable and require a fixed number of stages in their hardware architecture, leading to high computational complexity and power consumption, making them impractical for IoT and wearable devices, especially when dealing with varying filter kernel sizes.

Innovation Solution

A scalable bit-pipelined architecture for rank filters is introduced, allowing dynamic adjustment of the number of stages and using a flag bit to enable early stopping of the filtering calculation, reducing power consumption and maintaining bit precision even when truncating the pipeline.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the filter kernel size is increased to improve noise removal capability, then the filtering performance is improved, but the computational complexity and hardware area increase dramatically

Engineering Contradiction:
Improvenoise removal capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The rank filter is divided into multiple pipeline stages, where each stage processes a specific bit position. This segmentation allows the filter to handle large kernel sizes by breaking down the complex sorting operation into simpler, parallel bit-level comparisons across stages, reducing the computational complexity while maintaining noise removal effectiveness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pipeline architecture allows dynamic configuration of the number of stages and parallel processing units. This enables the system to adapt to different kernel sizes by adjusting the pipeline depth and width, providing scalability without requiring complete redesign of the hardware architecture.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the filter kernel size is increased to improve noise removal capability, then the filtering performance is improved, but the hardware area increases dramatically

Engineering Contradiction:
Improvenoise removal capabilityVSAvoidhardware area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By segmenting the rank filter into bit-level pipeline stages, each handling a specific bit position, the hardware area is distributed across multiple small units rather than requiring one large sorting network. This segmentation enables efficient space utilization while maintaining the capability to handle large kernel sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a traditional word-level sorting approach to a bit-level pipeline approach, effectively adding a time dimension to the processing. Multiple bit positions are processed sequentially through the pipeline, allowing the system to handle larger kernels without proportionally increasing the spatial hardware area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If a fixed number of pipeline stages is used to simplify hardware architecture, then the device complexity is reduced, but the adaptability to different filter kernel sizes is lost

Engineering Contradiction:
Improvehardware architecture simplicityVSAvoidscalability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The pipeline architecture incorporates dynamic control mechanisms that allow the number of active stages and parallel units to be adjusted based on the required kernel size. This dynamic configuration maintains hardware simplicity while providing scalability, as the same base architecture can be adapted to different applications by enabling or disabling specific pipeline stages.

Inventive Principle:
Principle #15Dynamics

4Measurement precision

If all pipeline stages are executed to ensure accurate median calculation, then the measurement precision is maintained, but the power consumption increases

Engineering Contradiction:
Improvemedian calculation accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The pipeline architecture allows partial execution of stages based on early termination conditions. When the median value is determined with sufficient precision before all stages complete, the remaining stages can be skipped, reducing power consumption while maintaining adequate accuracy for the application.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system incorporates feedback mechanisms that monitor the convergence of the median calculation during pipeline execution. When the output stabilizes or reaches the required precision threshold, the feedback signal triggers early termination of subsequent stages, optimizing power consumption while preserving measurement accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9928583B2Scalable rank filter
Publication Date: 2018.03.27 INTEL CORP
  • US9928583B2 patent drawing
  • US9928583B2 patent drawing
  • US9928583B2 patent drawing

AI summary

A scalable rank filter and method that performs rank filtering based on input data samples are disclosed. In one embodiment, the rank filter comprises a pipeline that receives input data samples and generates an output based on the input data samples as a result of completing execution of the pipeline. The rank filter includes output logic to determine the output prior completing execution of the pipeline and outputs an indication of a median.