Bit Plane Encoding Reduces SLM Memory Requirements
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Solution Overview
Problem
Spatial light modulators (SLMs) require significant memory to store bit planes, making it economically unfeasible to embed dynamic random access memory (DRAM) within the image processing and control circuitry, despite the potential for cost savings and reduced complexity.
Innovation Solution
A bit plane encoding/decoding system that generates bit planes on-the-fly from encoded pixel data, reducing the need for storing bit planes and allowing for the use of embedded DRAM, which includes a memory configured to store pixel data and bit plane decoding circuitry to transform the pixel data into bit planes based on signals from a sequence controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external DRAM chips are used to store bit planes, then memory capacity is sufficient, but device complexity and cost increase
Solution Approach 1:
The patent merges the DRAM memory function with the image processing circuitry by integrating DRAM cells directly into the pixel circuit structure. The same transistor and capacitor components that control pixel operation are also used to store bit plane data, eliminating the need for separate external DRAM chips and reducing overall device complexity while maintaining sufficient memory capacity.
Solution Approach 2:
The patent makes the pixel circuit components multi-functional by enabling them to serve both as pixel control elements and as memory storage elements. The transistor gate and capacitor structures that normally control light modulation are also configured to store bit plane data, allowing a single component to perform multiple functions and reduce the need for additional dedicated memory components.
2Reliability
If bit planes are stored in memory, then image data is available for display, but memory size requirements become economically unfeasible for embedding
Solution Approach 1:
The patent segments the bit plane data storage across multiple pixel circuits rather than requiring a single large dedicated memory block. Each pixel circuit stores a portion of the bit plane data in its transistor/capacitor structure, distributing the memory burden across many small units. This segmentation makes the total memory capacity achievable through standard pixel circuit dimensions, enabling economically feasible embedding.
Solution Approach 2:
The patent utilizes the spatial dimension within the pixel circuit structure itself for memory storage, rather than adding memory in a separate external dimension. By embedding DRAM cells within the existing pixel circuit footprint and using the same physical structures for dual purposes, the solution achieves memory integration without increasing the overall device area or manufacturing complexity.
3Manufacturing precision
If more memory is embedded, then image artifacts are reduced, but manufacturing cost and complexity increase
Solution Approach 1:
The patent enables the pixel circuit to serve itself by using its own transistor and capacitor structures for both pixel operation and memory storage. This self-service approach eliminates the need for additional dedicated memory components and complex interconnections between separate memory and processing units, reducing manufacturing complexity while providing sufficient memory capacity to reduce image artifacts.
Data Source
AI summary
A bit plane generating system, a method of generating a bit plane and an integrated circuit incorporating the system or the method. In one embodiment, the bit plane generating system includes: (1) a memory configured to store pixel data pertaining to an image to be displayed and (2) bit plane decoding circuitry coupled to the memory and configured to transform the pixel data into at least a portion of a bit plane in accordance with a signal received from a sequence controller.