Bit Prioritization for Non-Volatile Memory Error Correction
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Solution Overview
Problem
Non-volatile memory (NVM) devices face errors due to overlapping threshold voltage distributions, leading to inaccurate data reading, and existing error correction methods are inefficient in terms of time and power consumption.
Innovation Solution
A system that utilizes authentication functionality to identify and correct errors by prioritizing bits based on their likelihood of being erroneous, using a trial and error method to flip bits and verify corrections through margin read functionality, thereby reducing the overall correction cycle time and power expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells store n bits in a single cell using 2^n-1 threshold levels, then storage capacity increases, but the voltage difference between adjacent levels decreases making sensing error-prone
Solution Approach 1:
The patent applies preliminary action by performing margin reads before actual data reads to identify weak bits that are prone to errors. The system proactively detects bits with threshold voltages close to decision boundaries and prioritizes them for correction, preventing reading errors before they occur.
Solution Approach 2:
The system uses self-service by leveraging its own authentication functionality and margin read capabilities to automatically detect and correct its own errors. The memory system performs self-diagnosis through margin reads and self-correction by flipping identified weak bits, eliminating the need for external repair mechanisms.
2Reliability
If trial and error methods are used to correct memory errors by flipping bits, then error correction is achieved, but time and power consumption increase
Solution Approach 1:
The patent applies local quality by focusing correction efforts only on locally identified weak bits rather than uniformly checking all bits. The margin read functionality identifies specific bits with threshold voltages near decision boundaries, and the system prioritizes correcting only these local problem areas, reducing overall correction time and power consumption.
Solution Approach 2:
The system performs preliminary identification of weak bits through margin reads before attempting corrections. By pre-sorting and prioritizing bits based on their error likelihood, the system avoids unnecessary trial-and-error attempts on strong bits, significantly reducing the time and power required for error correction.
3Quantity of substance
If existing authentication functionality is used for error correction, then additional memory overhead is avoided, but the correction process must rely on trial and error methods
Solution Approach 1:
The patent applies universality by making the authentication functionality multi-functional. The existing authentication mechanism, originally designed for verifying data integrity, is repurposed to also perform error detection and correction. This allows the system to achieve error correction without adding dedicated correction hardware or extra memory structures.
Solution Approach 2:
The system uses self-service by leveraging its own authentication functionality to perform error correction. The authentication mechanism identifies erroneous bits and the system automatically corrects them using the same authentication infrastructure, eliminating the need for separate correction mechanisms and reducing overall system complexity.
Data Source
AI summary
System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.