Bit Processing Circuitry for Flexible Permutation Control

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Solution Overview

Problem

Existing bit processing systems require complex and inflexible control circuitry for bit-level permutation operations, which limits their ability to perform multiple instances of bitwise processing efficiently and flexibly.

Innovation Solution

The implementation of a set of bit processing circuitries with controllable bit shifting and inhibit functions, allowing for selective propagation of inhibit control signals between circuitries, enabling multiple instances of bitwise processing using a common set of circuitries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated control circuitry is used for a particular permutation operation, then the bit shifting operation can be performed reliably, but the device complexity increases and flexibility is reduced

Engineering Contradiction:
Improvebit shifting operation reliabilityVSAvoidcontrol circuitry complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal bit processing circuitry that can perform multiple permutation operations through a common set of n bit processing circuitries. Each circuitry can be configured to implement different permutation operations by changing control signals, eliminating the need for dedicated control circuitry for each operation while maintaining reliability through systematic control mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control circuitry is designed to be dynamically reconfigurable, allowing the same hardware to adapt to different permutation operations by changing control parameters. This dynamic approach reduces device complexity compared to static dedicated circuitry while maintaining operational reliability through controlled reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Reliability

If dedicated control circuitry is used for a particular permutation operation, then the bit shifting operation can be performed reliably, but the adaptability is reduced

Engineering Contradiction:
Improvebit shifting operation reliabilityVSAvoidpermutation operation flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal bit processing architecture where n bit processing circuitries can implement multiple permutation operations. The system achieves adaptability by allowing different control signal configurations to direct the same hardware to perform various permutation tasks, while reliability is maintained through systematic control and coordination of the circuitries.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system employs dynamic reconfiguration capabilities where control signals can change the operational mode of the bit processing circuitries on the fly. This allows the same hardware to adapt to different permutation operations without physical reconfiguration, enhancing versatility while maintaining reliability through controlled transitions.

Inventive Principle:
Principle #15Dynamics

3Reliability

If multiple instances of bitwise processing are performed using separate circuitries, then each operation can be executed independently, but the device complexity and number of components increase

Engineering Contradiction:
Improveoperation independenceVSAvoidnumber of components
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple bit processing operations into a single unified array of n bit processing circuitries. These circuitries can handle multiple instances of bitwise processing simultaneously or sequentially by sharing common resources and control mechanisms, reducing the total number of components while maintaining operational independence through proper control signal management.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified bit processing circuitry is designed to be multi-functional, capable of executing multiple instances of bitwise processing operations. The same n circuitries can be reused across different operations by reconfiguring control signals, eliminating the need for separate dedicated circuitries for each operation while preserving operational independence.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If multiple instances of bitwise processing are performed using separate circuitries, then each operation can be executed independently, but the number of components needed increases

Engineering Contradiction:
Improveoperation independenceVSAvoidnumber of components
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple bit processing functions into a single integrated array of n bit processing circuitries. This merging approach allows multiple instances of bitwise processing to share common hardware resources, significantly reducing the total number of components needed while maintaining operation independence through controlled access and coordination mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bit processing circuitry is designed as a universal resource that can serve multiple operation instances. By making the circuitry multi-functional and reusable across different operations, the system reduces component quantity while preserving the ability to execute operations independently through proper control and timing mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10366741B2Bit processing
Publication Date: 2019.07.30 ARM LTD
  • US10366741B2 patent drawing
  • US10366741B2 patent drawing
  • US10366741B2 patent drawing

AI summary

Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.