Bit Rate Matching Layout With Unified Storage and Sequential Readout
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Solution Overview
Problem
The existing bit rate matching processes in mobile communication systems, particularly in LTE, are complex and energy-intensive due to the need for multiple storage buffers and intricate address multiplexing, leading to increased power consumption and system complexity.
Innovation Solution
A serial and parallel processing method for bit rate matching that simplifies storage by interleaving system bit and check data streams in a dual-port storage, allowing for efficient interleaving and puncturing, reducing the number of storage interfaces and processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware processing is performed according to the protocol steps with multiple storages and interleaved-reading, then the bit rate matching function is achieved, but the device complexity and power consumption increase dramatically
Solution Approach 1:
The patent merges the system bit storage and check bit storage into a single storage unit, eliminating the need for separate storages. The check bits are stored contiguously after the system bits in the same storage space, simplifying the storage structure while maintaining all necessary functions.
Solution Approach 2:
The single storage unit serves multiple functions: storing system bits, storing check bits, and providing both sequential and interleaved reading capabilities. This multi-functional design replaces the need for multiple specialized storages and reduces overall system complexity.
2Reliability
If hardware processing is performed with constant address conversion and interleaved-reading, then the bit rate matching is implemented, but power consumption increases
Solution Approach 1:
The patent performs preliminary organization of data in the storage unit during the writing phase, placing system bits and check bits in specific positions. This preliminary arrangement enables subsequent reading operations to use simple sequential access patterns rather than complex interleaved patterns, reducing power consumption during reading.
Solution Approach 2:
Instead of using complex interleaved-reading patterns to achieve rate matching, the patent inverts the approach by organizing data in a simple sequential structure during writing, and then using simple sequential reading with selective skipping to achieve the same rate matching effect, thereby reducing power consumption.
3Adaptability or versatility
If software implementation is used for rate matching, then processing flexibility is achieved, but processor requirements and costs increase dramatically
Solution Approach 1:
The patent replaces the software-based mechanical processing system with a hardware-based system that uses simple sequential access patterns. The hardware implementation uses basic read/write operations on a single storage unit, eliminating the need for complex software algorithms and high-performance processors while maintaining adaptability through configurable reading patterns.
4Ease of manufacture
If three separate storages are used for system bit, check 1, and check 2 data, then data organization is achieved, but the number of storage interfaces and complexity increase
Solution Approach 1:
The patent combines three separate storage units into a single storage unit where system bits and check bits are stored in a contiguous structure. This merging reduces the number of storage interfaces from three to one while maintaining clear data organization through positional encoding.
Solution Approach 2:
The patent transitions from a multi-dimensional storage architecture (three separate storages) to a single-dimensional structure (one storage with contiguous allocation). Data is organized along a single linear dimension with system bits occupying the first portion and check bits occupying the second portion, simplifying the interface requirements.
Data Source
AI summary
A serial processing method and a parallel processing method of bit rate matching and apparatuses thereof are disclosed in the present invention. The serial processing method includes: receiving a system bit data stream, a check 1 data stream and a check 2 data stream, performing interleaving processing on the system bit data in the received system bit data stream, and caching in a first buffer cache of a storage; simultaneously performing interleaving processing on the corresponding data in the received check 1 data stream and the received check 2 data stream, and caching the data on which the performing interleaving processing is performed in a second buffer of the storage; and reading valid data from the storage and implementing the rate matching.