Bit Rate Processor Scaling Circuit for TDSCDMA Interference Management
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Solution Overview
Problem
TDSCDMA wireless systems face limitations in achieving high computation speed, flexibility, and programmability due to the complexity of joint detection algorithms and the need to manage multiple access interference, which affects system capacity and user separation.
Innovation Solution
A bit rate processor architecture comprising a front end processor, a transport channel buffer, and a back end processor with a scaling circuit, which processes physical channel data to generate transport channel bits, addressing the limitations by optimizing computation stages and buffer memories to handle multiple users and interference effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If joint detection algorithms are used to process all users in parallel and include interference information, then system capacity and user separation efficiency are improved, but device complexity and computational load increase exponentially
Solution Approach 1:
The joint detection process is segmented into multiple stages: initial detection of strong signals, interference cancellation, and subsequent detection of weaker signals. This divides the complex exponential complexity problem into manageable linear complexity stages, maintaining user separation efficiency while reducing overall computational burden.
Solution Approach 2:
An interference cancellation component acts as an intermediary between the receiver and decoder, preprocessing the received signal by removing identified interference before passing cleaned signals to the decoder. This mediator reduces the computational complexity of the main detection algorithm while preserving detection accuracy.
2Device complexity
If rake receivers are used for detection, then device complexity is reduced, but measurement precision and interference characterization capability deteriorate
Solution Approach 1:
The system applies partial joint detection by fully characterizing and canceling only the strongest interferers, rather than attempting to perfectly characterize all interference sources. This partial action maintains acceptable measurement precision for dominant signals while keeping device complexity low, avoiding the exponential complexity of complete joint detection.
3Adaptability or versatility
If programmable digital signal processors are used for baseband processing, then adaptability and flexibility are improved, but computation speed and processing capability deteriorate
Solution Approach 1:
The baseband processing function is segmented into fixed-function hardware blocks (correlators, interference cancellers) and programmable control logic. The computationally intensive signal processing operations are implemented in fixed hardware for speed, while the programmable portion handles only configuration and control, achieving both high computation speed and adaptability.
Solution Approach 2:
The patent replaces general-purpose programmable digital signal processing with specialized hardware circuits implemented in ASIC or FPGA. This substitution of mechanical/software-based processing with dedicated electronic hardware achieves the required computation speed while maintaining flexibility through reconfigurable logic and programmable parameters.
4Productivity
If ASICs are used for baseband processing, then computation speed is improved, but adaptability and flexibility for different applications deteriorate
Solution Approach 1:
The ASIC incorporates multiple functional blocks that can be configured for different processing tasks through programmable parameters and control logic. The universal correlator, interference canceller, and decoder blocks can handle various CDMA variants and processing algorithms, providing multi-functionality that maintains high computation speed while enabling adaptability across different applications.
Solution Approach 2:
The ASIC includes reconfigurable elements such as programmable filters, adjustable threshold levels, and configurable interference cancellation parameters. These dynamic elements allow the fixed hardware to adapt its behavior for different applications and signal conditions, bridging the gap between the speed of ASICs and the flexibility of programmable processors.
Data Source
AI summary
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.