Bit Recovery System for MRAM Hard Failure Correction
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Solution Overview
Problem
Data errors in magnetoresistive random-access memory (MRAM) devices, such as those caused by insulating layer breakdown, can lead to hard failures that existing error correction codes (ECC) cannot correct, requiring redundant or mirrored memory devices for recovery.
Innovation Solution
A bit recovery system incorporating a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory, which stores additional error correction data, allowing for quicker error correction without the need for redundant or mirrored memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant or mirrored memory devices are used to correct hard failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction functionality into two distinct parts: a primary ECC module for correcting standard errors, and a secondary BR memory for storing and applying bit recovery data for hard failures. This segmentation allows each component to specialize in specific error types, improving overall reliability without requiring complete redundant memory systems.
Solution Approach 2:
The patent implements preliminary action by pre-storing bit recovery data in the BR memory before hard failures occur. When insulating layer breakdown or other hard failures happen, the system can immediately retrieve and apply the pre-stored recovery data, eliminating the need for complex real-time redundancy management while maintaining high reliability.
2Manufacturing precision
If traditional ECC modules are used for error correction, then manufacturing precision is maintained, but productivity decreases due to inability to correct hard failures
Solution Approach 1:
The patent creates a universal error correction system where the BR memory serves multiple functions: storing bit recovery data for hard failures, maintaining manufacturing precision through accurate error correction, and improving productivity by enabling correction of both soft and hard errors within a single integrated architecture.
Solution Approach 2:
The BR memory acts as an intermediary between the primary ECC module and the resistance-based memory device. It receives and stores bit recovery data, then provides it back to correct hard failures, enabling the system to maintain manufacturing precision while significantly improving productivity by handling error types that traditional ECC cannot correct.
3Reliability
If insulating layer breakdown occurs in MTJ devices, then data storage capability is affected, but the breakdown mechanism itself cannot be prevented
Solution Approach 1:
The patent converts the harmful effect of insulating layer breakdown into a beneficial outcome by pre-storing the correct bit values in BR memory before breakdown occurs. When breakdown happens, the system retrieves and applies this stored data, transforming an irreversible physical degradation into a correctable logical error, thereby maintaining data storage capability despite the unavoidable breakdown mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables recovery from hard failures and faster data error correction within electronic devices, enhancing their operational reliability and efficiency.
Implementation Method 1
MTJ devices include a free layer and a fixed layer and may store data based on an orientation of the free layer relative to the fixed layer
Implementation Method 2
A MRAM device may include magnetic tunnel junction (MTJ) devices as storage elements
Implementation Method 3
The logic one may be detected during a read operation by determining that a resistance of the MTJ device is in a second, higher range (because a MTJ device in the anti-parallel state has higher resistance than a MTJ device in the parallel state)
Data Source
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AI summary
A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.