Bit-Reduced Verification for Memory Arrays Using Address Sampling
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Solution Overview
Problem
The complexity of semiconductor device components, particularly memory arrays, poses challenges in verification processes due to their intricate designs and shrinking transistor sizes, leading to inefficiencies in current verification methods such as simulation-based validation and formal verification, which are time-consuming and data-intensive.
Innovation Solution
The implementation of bit-reduction techniques during verification, where a sampled address is used instead of data sampling, reducing the number of bits communicated or generated per clock cycle, replicating the hardware delay and maintaining physical memory array behavior while significantly reducing the number of bits communicated, allowing for more efficient and robust verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation-based validation or formal verification is used to verify memory array functionality, then verification completeness is improved, but verification time and data communication volume increase significantly
Solution Approach 1:
The patent extracts only the essential verification elements (address bits and hit/miss indicators) from the complete memory verification process, separating them from the full data set. This allows verification to focus on critical functional aspects while eliminating unnecessary data communication overhead.
Solution Approach 2:
The patent applies different verification strategies to different parts of the memory system. Instead of uniformly verifying all memory operations with full data communication, it uses bit-reduced verification for address matching and hit/miss determination, while maintaining detailed verification only where necessary for functional correctness.
2Measurement precision
If full data communication is used during verification to replicate hardware read operations, then verification accuracy is improved, but data communication volume and processing complexity increase
Solution Approach 1:
The patent creates a simplified model (bit-reduced memory array) that replicates the essential behavior of the full memory array. This model copies only the critical verification characteristics (address matching and hit/miss logic) while omitting unnecessary data details, enabling accurate verification with reduced data communication.
Solution Approach 2:
Instead of reducing verification accuracy to decrease data communication volume, the patent inverts the approach by using clever sampling techniques that maintain verification accuracy while naturally reducing data communication. The address sampling and hit/miss indicator generation provide full verification coverage without requiring full data set communication.
3Reliability
If traditional verification methods are used to handle complex memory array designs, then verification thoroughness is improved, but verification tool complexity and resource requirements increase
Solution Approach 1:
The patent changes the verification parameters from full data communication to bit-reduced communication with address sampling. This parameter change simplifies the verification tool requirements while maintaining thoroughness, as the essential functional behavior can be verified through address matching and hit/miss determination without processing complete data sets.
Data Source
AI summary
Bit-reduction in a verification processes for memory arrays is disclosed. Properties are determined for verification of a circuit that includes a memory array. Circuit data for the circuit is received in a verification environment. When it is determined that the circuit includes a memory array, an address for the memory array is sampled as part of a read operation during verification for the circuit. A determination may be made that the circuit is in compliance with a property of the properties based at least in part on compliance of the read operation with a predetermined model. The sampling of the address replicates a delay expected in physical read operation of the memory array, but with reduced bits communicated or generated per cycle in the verification process because output data is not sampled contrasting the physical read operation.