Bit-Reduction for ML-Based Scan Chain Diagnosis
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Solution Overview
Problem
Conventional methods for scan chain diagnosis in integrated circuits face challenges in accurately identifying un-modeled faulty behavior in scan chains, particularly due to the large input vectors required for machine learning models, which exceed the capacity of typical computer systems.
Innovation Solution
A method involving bit-reduction techniques such as pattern-based and cycle-based bit compression, combined with machine learning models like Artificial Neural Networks, to preprocess and compress test response patterns for training, enabling the identification of defective scan cells in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If machine learning models are used for chain diagnosis with full test response patterns, then diagnostic accuracy is improved, but computational resource requirements become unmanageably large
Solution Approach 1:
The patent extracts only the relevant failing bits from the complete test response patterns to form a reduced input vector for machine learning models. Instead of using all test response data, the system identifies and extracts only the bits that actually fail, dramatically reducing the input vector size while maintaining diagnostic accuracy.
Solution Approach 2:
The patent segments the large test response patterns into individual bits and further groups them by failure characteristics. This segmentation allows the system to process only the relevant failing bits separately, reducing the overall computational burden while preserving the diagnostic information needed for accurate chain diagnosis.
2Measurement precision
If complete test response patterns are used for training machine learning models, then diagnostic resolution is improved, but training time and computational cost increase significantly
Solution Approach 1:
The patent extracts only the essential failing bit information from complete test response patterns for model training. By extracting only the relevant failure data rather than using complete patterns, the training process becomes computationally feasible while maintaining diagnostic resolution.
Solution Approach 2:
The patent applies partial action by using only the necessary portion of test response data (the failing bits) rather than the complete patterns. This partial data approach is sufficient for achieving accurate chain diagnosis while dramatically reducing training time and computational cost.
3Measurement precision
If hardware-based scan chain diagnosis methods are used, then defect isolation accuracy is improved, but additional hardware requirements increase device complexity
Solution Approach 1:
The patent replaces hardware-based diagnosis methods with a software-based machine learning approach. Instead of using additional physical hardware for defect isolation, the system uses computational algorithms that process test response data to identify faulty scan chains, thereby maintaining diagnostic accuracy while reducing hardware complexity.
Solution Approach 2:
The patent introduces machine learning models as an intermediary between test response data and defect identification. This intermediary computational layer replaces the need for additional hardware components, enabling accurate defect isolation through software-based pattern recognition rather than hardware-based detection.
Data Source
AI summary
Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.