Post-Processor Bit Reliability Using Error Correction Constraints
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Solution Overview
Problem
Current error correction systems for magnetic hard disk drives, which include Viterbi detectors and parity post-processors, do not provide sufficient protection against error events and fail to deliver high-quality bit reliability information.
Innovation Solution
The implementation of a soft-input-soft-output (SISO) detector and post-processor system that generates bit reliabilities by finding the most likely combinations of error events satisfying error correction constraints, using log-likelihood ratios (LLR) to refine bit estimates and improve data sequence accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If linear block code parity constraints and longer target response are incorporated into the Viterbi detector, then error correction capability is improved, but device complexity increases exponentially
Solution Approach 1:
The system divides error correction into two separate stages: first the Viterbi detector processes the signal, then a parity post-processor independently applies parity constraints to correct errors. This segmentation avoids the exponential complexity of integrating constraints directly into the Viterbi detector while maintaining error correction capability.
Solution Approach 2:
A parity post-processor is introduced as an intermediary component between the Viterbi detector and the final data output. This mediator applies parity constraints separately, improving error correction without requiring modifications to the Viterbi detector itself, thus avoiding exponential complexity increase.
2Reliability
If a parity post-processor is added to the Viterbi detector, then error correction is improved, but bit reliability information quality is insufficient
Solution Approach 1:
The system uses feedback by iteratively refining bit reliability estimates. The post-processor generates initial reliability information, which is then used to improve subsequent error correction passes, progressively enhancing both error correction capability and bit reliability information quality.
Solution Approach 2:
The post-processor dynamically adjusts its error correction approach based on the reliability information from the Viterbi detector. By adapting to the detected error patterns and reliability metrics, the system improves bit reliability information quality while maintaining error correction effectiveness.
3Speed
If conventional error correction systems are used, then processing speed is maintained, but protection against error events is insufficient
Solution Approach 1:
The parity post-processor performs preliminary error correction by identifying and correcting errors based on parity constraints before final data output. This preliminary action enhances error event protection without significantly impacting processing speed, as the correction is applied efficiently in a separate stage.
Data Source
AI summary
Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.