Bit Remapping System for Memory Error Correction
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Solution Overview
Problem
As semiconductor processes scale, semiconductor devices become less reliable and prone to hardware errors, requiring redundant memory rows for error correction, which consumes significant area and is costly in certain applications.
Innovation Solution
A bit remapping system that includes a controller with a counter and a remapping device, which stores bit error counts and remaps addresses to correct memory errors using less redundant memory, such as a single memory cell, even when the memory array lacks redundant rows or columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant rows are used to correct memory errors, then memory reliability is improved, but memory area consumption increases
Solution Approach 1:
The patent segments the error correction function into two parts: (1) a small counter circuit that monitors bit errors for each address, and (2) a remapping mechanism that redirects failed addresses to alternative locations. This segmentation allows error correction without requiring full redundant memory rows, thus reducing area while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of error correction from using spatial redundancy (full redundant rows) to using temporal monitoring and dynamic remapping (counter-based detection and address redirection). This parameter change enables correction of recurring bit errors with minimal area overhead.
2Reliability
If redundant rows are used to correct memory errors, then memory reliability is improved, but device cost increases
Solution Approach 1:
By segmenting the error correction approach into lightweight counter circuits and remapping logic, the patent avoids the high cost of full redundant memory rows while maintaining reliability, thus reducing device cost.
Solution Approach 2:
The patent uses inexpensive counter circuits and remapping mechanisms instead of expensive redundant memory rows. The counters are simple digital logic elements that can detect and track bit errors without requiring additional memory resources, thereby reducing manufacturing cost.
3Area of stationary object
If a single memory cell is used for error correction instead of redundant rows, then memory area is reduced, but error correction capability must be enhanced
Solution Approach 1:
The patent introduces counter circuits as intermediary elements that monitor bit errors and trigger remapping operations. These counters act as mediators between the memory array and the remapping logic, enabling area-efficient error correction while managing complexity through a clear detection-response mechanism.
Solution Approach 2:
The patent replaces the physical redundancy mechanism (additional memory rows) with a logical control mechanism (counters and remapping logic). This substitution reduces area while concentrating the correction function in dedicated control circuitry, balancing area reduction with controlled complexity.
Data Source
AI summary
A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.