Bit Reordering Controller for NAND Bus Line Crossing Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SSD systems face manufacturing cost increases due to the need for extra vertical interconnect accesses and board layers caused by crossing-over of bus lines between NAND dies and the NAND controller, which is not efficiently addressed by current bit reordering methods that cannot arbitrarily reorder bits.
Innovation Solution
A memory device with a controller that receives an input bit sequence, identifies the physical location of non-volatile memory elements, determines the correspondence between the input and output bit orders, and generates an output bit sequence to reorder bits arbitrarily, using a look-up table and swap unit to avoid bus line crossing-over.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If swap circuit is integrated in each NAND die for bit reordering, then bit reordering can be performed at the bus interface, but arbitrary bit order reordering cannot be achieved
Solution Approach 1:
A lookup table is introduced as an intermediary data structure that stores the correspondence between physical locations and bit orders. The controller queries this table to determine the appropriate bit reordering scheme, enabling flexible adaptation without modifying the hardware swap circuit design. This intermediary layer decouples the fixed hardware from the flexible reordering requirements.
Solution Approach 2:
The bit reordering scheme is made dynamic by allowing the controller to select different reordering patterns based on the physical location of NAND dies retrieved from the lookup table. Instead of a fixed swap circuit configuration, the system dynamically adjusts the bit reordering strategy according to the specific die being accessed, enabling arbitrary bit order reordering.
2Ease of operation
If bus lines are allowed to cross-over to connect NAND dies to controller, then connection flexibility is improved, but manufacturing costs increase due to extra vertical interconnect accesses and board layers
Solution Approach 1:
The system performs preliminary bit reordering at the bus interface before data enters the main processing path. By pre-reordering bits according to the physical location of each die (determined via lookup table), the system ensures that subsequent data processing operations can proceed without requiring complex bus line cross-overs or additional board layers, thus avoiding increased manufacturing costs.
Solution Approach 2:
The patent replaces the mechanical/physical solution of crossing bus lines with an electronic/software-based solution of bit reordering. Instead of physically routing bus lines in complex patterns that require extra VIAs and board layers, the system uses logical bit reordering controlled by the lookup table to achieve the same connectivity flexibility without the associated manufacturing complexity and cost.
Data Source
AI summary
The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.