Bit-Reversed Polar Code Decoding for Lower Latency Parallelism
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Solution Overview
Problem
Polar encoders and decoders suffer from low coding/decoding throughput and high latency due to the inherent data dependencies in the serial cancellation decoding algorithm, limiting parallelization in conventional polar encoding and decoding techniques.
Innovation Solution
Implementing a semi-parallel bit-reversal technique at the polar encoder and/or decoder to reduce latency by applying bit-reversal permutation matrices and selecting memory banks based on the bit-reversed order of indices, enabling parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial cancellation decoding algorithm is used for polar decoding, then decoding accuracy is maintained, but decoding latency is high and throughput is low
Solution Approach 1:
The polar code block is divided into multiple sub-blocks that can be decoded in parallel. The received signal is segmented into multiple segments, each processed by separate decoding units simultaneously, breaking the sequential dependency of the conventional serial cancellation decoding algorithm while maintaining decoding accuracy through coordinated processing of all segments.
Solution Approach 2:
The invention transitions from one-dimensional sequential processing to multi-dimensional parallel processing by introducing multiple decoding units operating simultaneously on different segments. This dimensional expansion allows the system to overcome the inherent seriality constraint while preserving the error correction capabilities of polar codes.
2Productivity
If serial cancellation decoding algorithm is used, then correct error correction is achieved, but coding/decoding operations cannot be parallelized
Solution Approach 1:
The encoder output is segmented into multiple parallel streams that can be processed independently by different decoding units. This segmentation enables parallelization of the coding/decoding operations while maintaining the error correction functionality through the coordinated processing of all segmented streams.
Solution Approach 2:
The received signal is pre-processed and segmented into multiple independent segments before entering the parallel decoding units. This preliminary segmentation action prepares the data for parallel processing, reducing the complexity of coordination between decoding units while enabling simultaneous error correction across all segments.
3Reliability
If conventional polar encoding/decoding is implemented, then error correction capability is maintained, but latency is high due to sequential processing
Solution Approach 1:
The error correction process is segmented into multiple parallel operations where different segments of the code block are corrected simultaneously by separate decoding units. This maintains the error correction capability for all segments while reducing the overall latency through parallel execution of correction operations.
Solution Approach 2:
Multiple decoding units operate continuously and simultaneously on different segments of the received signal, eliminating the idle time inherent in sequential processing. This continuous parallel operation maintains comprehensive error correction coverage while significantly reducing the total time required for encoding and decoding operations.
Data Source
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AI summary
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive a signal from a transmitter device, the signal including at least in part m consecutive elements, determine indices associated with each of the m consecutive elements, each of the m consecutive elements associated with a different index, bit reverse a binary sequence associated with each of the m consecutive elements, each of the m consecutive elements include a different binary sequence, determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m consecutive elements and write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.