Bit-Reversed Polar Code Encoding for Lower Decoding Latency
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Solution Overview
Problem
Conventional polar encoding and decoding techniques suffer from high latency due to the inherent data dependencies in serial cancellation algorithms, limiting the exploitation of parallelization and resulting in low coding/decoding throughput in wireless communication systems.
Innovation Solution
Implementing a semi-parallel bit-reversal technique at the polar encoder and decoder to reduce latency by applying a bit-reversal permutation matrix and selecting memory banks based on the most significant log2(m) bit, allowing for parallel processing and reduced computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial cancellation decoding algorithm is used for polar codes, then decoding accuracy is maintained, but latency increases and throughput decreases
Solution Approach 1:
The patent segments the polar code decoding process into multiple parallel processing units, each handling a portion of the codeword. The serial cancellation algorithm is divided into parallel stages where different processing elements can simultaneously work on different segments of the input data, thereby increasing throughput while maintaining the essential cancellation operations needed for accurate decoding.
Solution Approach 2:
The patent introduces a new dimensional approach by organizing the decoding process in a tree-structured parallel architecture rather than a linear serial sequence. This dimensional transformation allows multiple decoding operations to occur simultaneously at different levels of the tree, converting a time-sequential process into a spatially-parallel one that reduces latency.
2Reliability
If serial cancellation decoding algorithm is used for polar codes, then decoding accuracy is maintained, but device complexity increases due to inability to parallelize
Solution Approach 1:
The patent segments the complex serial cancellation algorithm into modular parallel processing units, each implementing a simplified version of the cancellation operation. This segmentation reduces the computational burden on each individual unit while distributing the overall complexity across multiple identical or similar modules, making the implementation more manageable and potentially more reliable.
Solution Approach 2:
The patent creates multiple copies of the same parallel processing unit, each configured to handle a specific segment of the decoding task. These identical copies ensure consistent and accurate processing across all data segments, maintaining decoding reliability while the parallel architecture itself manages the distribution of computational complexity.
Data Source
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AI summary
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In addition, the apparatus may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. Further, the apparatus may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In addition, the apparatus may write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.