Bit Scan Circuit for Non-Volatile Memory
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Solution Overview
Problem
Existing flash memory systems face inefficiencies in scanning large N-bit strings for logic '1's or '0's during programming operations, which can be time and hardware intensive, especially when the data page size is substantial, such as 10^5 bits.
Innovation Solution
A bit scan circuit is implemented with N scan blocks organized into groups, utilizing independent clock signals and token latches to efficiently count the number of bits with a predetermined binary value by selectively gating an input clock signal based on tag bits, allowing for accurate counting over two clock cycles using a single data latch per scan block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional scanning methods are used to count logic '1's or '0's in large N-bit strings during programming operations, then the scanning operation can be performed, but the time and hardware resources required become excessive
Solution Approach 1:
The N-bit string is divided into multiple groups, with each group processed by a dedicated scan block. This segmentation allows parallel processing of different bit segments simultaneously, significantly reducing the total scanning time compared to sequential processing of the entire string.
Solution Approach 2:
The patent introduces a time dimension by using multiple clock cycles (first clock signal and second clock signal) to process different aspects of the scanning operation. The first clock cycle loads data and performs initial processing, while the second clock cycle completes the counting operation, effectively using temporal dimension to accelerate the scanning process.
2Productivity
If traditional scanning methods are used to count logic '1's or '0's in large N-bit strings during programming operations, then the scanning operation can be performed, but the hardware resources required become excessive
Solution Approach 1:
Each scan block is designed as a universal unit that can process multiple bits within a group using the same circuitry. The scan blocks are replicated and organized in groups, allowing the same hardware design to be reused multiple times, reducing overall hardware complexity compared to having dedicated circuits for each bit.
Solution Approach 2:
Multiple scan blocks are organized into groups where they share common control logic and output aggregation circuits. The patent merges the functionality of individual scan blocks into group-level processing units, reducing redundant hardware components while maintaining parallel processing capabilities.
3Device complexity
If a single data latch per scan block is used with two clock cycles for counting, then hardware requirements are reduced, but the counting process becomes more complex
Solution Approach 1:
The scanning operation is divided into periodic phases using two distinct clock signals. The first clock signal handles data loading and initial state setup, while the second clock signal performs the actual counting operation. This periodic action simplifies the latch design by separating concerns into distinct time periods, making the overall process more manageable despite the multi-cycle nature.
Data Source
AI summary
A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.