Bit-Section Adders for Faster Neural Network Processing
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Solution Overview
Problem
Existing neural network processing apparatuses face challenges in efficiently performing large-scale add operations on complex input data in real-time, necessitating improved techniques for arithmetic operations like add and multiplication.
Innovation Solution
The method involves dividing input operands into bit sections, performing parallel or serial add operations using multi-input adders, and bit-shifting intermediate results to align with original bit positions, optimizing adder utilization and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If input operands are divided into bit sections and parallel add operations are performed, then processing speed is improved, but device complexity increases due to multiple adders required
Solution Approach 1:
The patent divides input operands into multiple bit sections (e.g., first bit section, second bit section, third bit section) and performs add operations on each section in parallel using separate adders. This segmentation enables simultaneous processing of different bit ranges, thereby improving processing speed while managing device complexity through structured organization of adder units.
2Manufacturing precision
If intermediate addition results are bit-shifted to align with original bit positions, then manufacturing precision is improved, but loss of time occurs due to additional shifting operations
Solution Approach 1:
The patent incorporates bit-shifting operations immediately after each parallel add operation to align intermediate results with their original bit positions before final summation. By performing this alignment action preliminarily and systematically, the patent ensures precise bit position matching in the final result while minimizing delays through efficient integration of shifting into the parallel processing flow.
3Productivity
If multiple adders are used for parallel add operations, then productivity is improved, but use of energy increases due to more active components
Solution Approach 1:
The patent segments the add operation into multiple parallel processes using separate adders for different bit sections. This segmentation increases productivity by enabling simultaneous processing but also increases energy consumption due to more active components. The patent balances this by organizing adders to process specific bit ranges efficiently and integrating their results systematically.
Solution Approach 2:
The patent designs the parallel adder structure to handle different bit sections with a unified approach, where each adder performs the same add operation on its designated bit range. This multi-functional arrangement improves productivity through parallelism while managing energy use by ensuring each adder is actively utilized for its specific function without wasted operations.
Data Source
AI summary
A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.