Bit-Sequence Check Code Processing for Ethernet Idle Blocks
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Solution Overview
Problem
In Ethernet data transmission, the insertion or deletion of idle blocks leads to a high probability of check errors due to mismatched check codes between sender and receiver, affecting transmission quality evaluation accuracy.
Innovation Solution
A check code processing method that integrates bits from each byte of a code block to generate a first sequence, which is then used to calculate a check code, ensuring that the check code remains consistent regardless of idle block insertion or deletion, and allowing for error detection in idle blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If check code is calculated by performing XOR operations on multiple bytes of code block, then check code can be generated, but insertion or deletion of idle block causes check code mismatch between sender and receiver
Solution Approach 1:
The patent changes the calculation parameter from operating on entire bytes to operating on individual bits within bytes. Specifically, it extracts the most significant bit (MSB) of each byte to form a first sequence, then performs XOR operations on these bit sequences. This parameter change makes the check code calculation insensitive to idle block insertion/deletion, as idle blocks contain specific bit patterns that result in predictable XOR outcomes, thereby maintaining check code consistency between sender and receiver despite variable idle block handling.
2Reliability
If traditional check code calculation is used, then calculation process is simple, but check error probability is very high due to idle block handling
Solution Approach 1:
The patent segments the check code calculation process into distinct stages: first extracting MSBs from each byte to form a first sequence, then performing XOR operations on these sequences to generate the final check code. This segmentation approach maintains relative simplicity while improving reliability, as each stage has a clear, deterministic function that handles idle blocks predictably.
Solution Approach 2:
The patent applies local quality by focusing the check code calculation on specific bit positions (MSBs) rather than treating all bytes uniformly. This localized approach to check code generation creates a calculation method that is inherently more robust to idle block variations, as the MSB patterns in idle blocks produce consistent XOR results, thereby increasing check success rate without requiring complex overall system changes.
3Measurement precision
If check code is generated using conventional methods, then generation process is straightforward, but insertion or deletion of idle block changes check code causing check failure
Solution Approach 1:
The patent changes the operational parameter from byte-level XOR operations to bit-level (MSB) extraction and XOR operations. This parameter change improves measurement precision for transmission quality evaluation, as the MSB-based check code is less susceptible to noise and idle block variations. The implementation remains relatively straightforward, requiring only modification of the bit extraction and XOR operation steps in the existing check code generation process.
Data Source
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AI summary
Disclosed in embodiments of this disclosure are a check code processing method, an electronic device and a storage medium. The check code processing method comprising: performing operations on m bits of the nth byte of a code block to obtain the nth bit of a first sequence; and performing operation on the first sequence of the code block with a same transmission period to obtain a check code.