Bit Sequence Encoding With Disparity and Run Length Limits

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Solution Overview

Problem

Existing data transmission methods in automobiles face challenges with high error rates, inefficiencies, and complex hardware requirements due to unfavorable disparity and run length in serial data streams, which can lead to baseline drift and unreliable clock recovery.

Innovation Solution

A method for generating a bit sequence with restricted disparity and run length by segmenting an arbitrary bit sequence into predefined segments and encoding each segment into sub-symbols using subsets of encoding units that actively control disparity, allowing for parallel processing and efficient transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional data transmission methods are used in automobiles, then the system can transmit data, but the error rate increases and reliability decreases due to unfavorable disparity and run length

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiderror rate
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the serial data stream into manageable units and applies specific coding schemes to control disparity and run length parameters. By dividing the data transmission into controlled segments with enforced coding rules, the system achieves reliable clock recovery and baseline stability without requiring complex hardware

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the data transmission by changing key parameters - specifically enforcing disparity control (balancing 1s and 0s) and run length limitations (preventing excessive consecutive identical bits). These parameter transformations eliminate baseline drift and enable reliable clock recovery, directly improving transmission reliability while maintaining simple hardware

Inventive Principle:
Principle #35Parameter changes

2Reliability

If disparity control is implemented to prevent baseline drift, then transmission reliability improves, but hardware complexity increases

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service disparity control where the coding scheme automatically balances 1s and 0s without requiring external control mechanisms. The encoding process inherently generates balanced output sequences, eliminating the need for complex external disparity management hardware while maintaining transmission reliability

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent applies preliminary coding transformations to the data stream before transmission, pre-establishing the desired disparity and run length properties. By performing these control actions in advance during the encoding phase, the system avoids needing complex real-time control hardware during transmission

Inventive Principle:
Principle #10Preliminary action

3Productivity

If efficient encoding schemes are used to reduce overhead, then data transmission efficiency improves, but error detection capability may be reduced

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoiderror detection capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent incorporates feedback mechanisms where the receiver detects coding violations (such as invalid disparity or run length patterns) and can request retransmission or correct errors. This feedback loop maintains high efficiency by only requiring minimal redundant transmissions while ensuring robust error detection through the structured coding framework

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12542699B2Efficiently transferable bit sequence with limited disparity
Publication Date: 2026.02.03 INOVA SEMICON
  • US12542699B2 patent drawing
  • US12542699B2 patent drawing
  • US12542699B2 patent drawing

AI summary

A method is provided for generating an efficiently transferable bit sequence with a limited disparity and a limited run length. A correspondingly configured system arrangement as well as to a computer program product and a memory-readable medium with control commands which execute the method are provided as well.