Bit-Serial Division and Square-Root Circuit Formal Verification
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Solution Overview
Problem
Current formal verification methods for bit-serial division and square-root circuit designs face significant runtime and memory issues, making it impractical to prove correctness using naive approaches.
Innovation Solution
The use of a bit-level solver to create and prove a set of properties for bit-serial division and square-root circuit designs, optimizing the verification process by avoiding word-level operations and leveraging bit-level solvers like binary decision diagrams or satisfiability-based solvers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If naive formal verification is used to prove correctness of division and square-root circuit designs, then verification completeness is improved, but runtime and memory consumption become prohibitively high
Solution Approach 1:
The patent segments the verification problem by introducing an intermediate model that separates the circuit design into two parts: the original circuit and a simplified iterative computation model. This intermediate model acts as a bridge that can be verified more efficiently, thereby reducing runtime consumption while maintaining verification completeness for the original circuit.
Solution Approach 2:
The patent introduces an intermediate iterative computation model as a mediator between the original circuit design and the verification process. This intermediate model is specifically designed to be more amenable to formal verification techniques, reducing memory consumption and runtime while preserving the correctness properties of the original circuit.
2Reliability
If naive formal verification is used to prove correctness of division and square-root circuit designs, then verification completeness is improved, but memory consumption becomes prohibitively high
Solution Approach 1:
The verification process is segmented into multiple stages: verifying the iterative computation model separately and then verifying the equivalence between the original circuit and the iterative model. This segmentation reduces memory consumption by avoiding the need to handle the entire verification problem in a single large-scale operation.
Solution Approach 2:
The intermediate iterative computation model serves as a memory-efficient mediator that captures the essential correctness properties without requiring the full complexity of the original circuit to be present simultaneously in memory during verification.
3Reliability
If exhaustive simulation is used to verify circuit design, then coverage is improved, but computational feasibility deteriorates
Solution Approach 1:
The patent replaces the mechanical exhaustive simulation approach with a formal verification system based on mathematical proofs. Instead of mechanically testing all possible inputs, the system uses logical reasoning and mathematical models to prove correctness, dramatically improving computational feasibility while maintaining high verification coverage.
Solution Approach 2:
The patent performs preliminary action by constructing an intermediate iterative computation model that encapsulates the correctness properties before the actual verification takes place. This preliminary modeling step simplifies the subsequent verification process, making it computationally feasible compared to direct exhaustive simulation.
Data Source
AI summary
Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root.