Bit-Serial Computing Device with Variable Significance Mapping
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Solution Overview
Problem
Bit-serial computing devices face challenges in enhancing output accuracy, particularly in neural networks, where existing technologies fail to effectively optimize the performance of multiply-and-accumulate (MAC) slices and scaler components.
Innovation Solution
A bit-serial computing device is designed with a computing circuit and scaler that includes multiple MAC slices, each calculating inner products of multiplier and multiplicand vectors with variable significance, and a test method to evaluate and reorder operations based on accumulated deviations to enhance accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit-serial computing is used in neural networks, then computational efficiency is improved, but output accuracy deteriorates
Solution Approach 1:
The patent applies dynamics by making the correspondence between significances and MAC slices variable rather than fixed. The system dynamically adjusts which MAC slice processes which significance level based on real-time performance evaluation, allowing the computing device to adapt its operation to maximize accuracy while maintaining bit-serial efficiency.
Solution Approach 2:
The patent implements feedback through the test method that evaluates MAC slice performance and uses accumulated deviations to determine relative accuracy relationships. This feedback loop allows the system to identify which MAC slices produce more accurate results and adjust the significance-to-MAC-slice mapping accordingly, thereby improving output accuracy without sacrificing computational efficiency.
2Device complexity
If fixed correspondence between significances and MAC slices is used, then device complexity is reduced, but output accuracy deteriorates
Solution Approach 1:
The system transitions from a static, fixed correspondence between significances and MAC slices to a dynamic, adjustable mapping. The correspondence can be reconfigured based on evaluated performance, allowing the system to optimize accuracy without requiring complex hardware changes - the complexity is managed through software-controlled reconfiguration rather than hardware complexity.
Solution Approach 2:
The patent changes the parameter of correspondence mapping from fixed to variable. By allowing the system to change which MAC slice handles which significance level based on performance characteristics, it achieves higher accuracy without fundamentally altering the hardware architecture, thus avoiding excessive device complexity.
3Measurement precision
If variable correspondence between significances and MAC slices is implemented, then output accuracy is improved, but device complexity increases
Solution Approach 1:
The feedback mechanism through test and evaluation provides intelligent control over the variable correspondence. Rather than requiring complex manual configuration, the system automatically evaluates MAC slice performance and determines optimal mappings based on accumulated deviation data, reducing the effective complexity burden on the user while maintaining accuracy benefits.
Solution Approach 2:
The system performs self-optimization through the test method that automatically evaluates MAC slice accuracies and determines the best significance-to-MAC-slice correspondences. This self-service capability reduces the need for external complex configuration and control mechanisms, achieving variable correspondence management with minimal additional device complexity.
Data Source
AI summary
A bit-serial computing device includes a computing circuit and a scaler. The computing circuit includes multiple MAC slices, and receives a multiplier vector and a multiplicand vector that contains multiple multiplicand inputs. Each multiplicand input contains multiple multiplicand segments that have different significances. The significances respectively correspond to the MAC slices. Correspondence between the significances and the MAC slices is variable. Each MAC slice calculates an inner product of the multiplier vector and a vector that is constituted by the multiplicand segments of the multiplicand inputs having the significance corresponding to the MAC slice. With respect to each MAC slice, the scaler multiplies the inner product that is calculated by the MAC slice by a weighting ratio that represents the significance corresponding to the MAC slice, so as to obtain a scaled inner product that corresponds to the MAC slice.