Bit-Serial Processing Element for Deep Neural Network Accelerator
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Solution Overview
Problem
Deep neural networks require adaptive bit-precision support for efficient inference operations, as the minimum bit-precision is variable across different layers and types, leading to inefficiencies in existing hardware resources.
Innovation Solution
A deep neural network accelerator incorporating lookup table based bit-serial processing elements that support various bit-precisions by reusing input features, allowing for improved power efficiency through the use of 1-bit weight values and efficient matrix multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low bit-precision processing elements are used, then throughput and energy efficiency are improved, but adaptive weight bit-precision capability is lost
Solution Approach 1:
The processing element dynamically adjusts its bit-precision handling capability through a control signal that enables or disables the inversion function. This allows the same hardware to adapt between different weight bit-precisions (1-bit or multi-bit) without physical reconfiguration, resolving the contradiction between fixed low-bit optimization and adaptive precision requirements
2Use of energy by stationary object
If 1-bit weight values are used, then power consumption is reduced, but computational precision is limited
Solution Approach 1:
The system changes the operational parameters of the processing element by using a control signal to switch between different weight bit-precision modes. When the control signal is at a first logic level, the element processes 1-bit weights with inversion capability; when at a second logic level, it processes multi-bit weights. This parameter switching allows the system to optimize power consumption for 1-bit operations while maintaining the capability for higher precision when needed
3Device complexity
If fixed-point arithmetic units are used, then hardware resource utilization is simplified, but energy efficiency decreases
Solution Approach 1:
The processing element is designed as a universal unit that can handle multiple weight bit-precisions (1-bit and multi-bit) through a single configurable architecture. By incorporating the inversion function controlled by a control signal, the element serves multiple purposes: it can process both 1-bit weights with sign inversion and multi-bit weights without inversion, eliminating the need for separate fixed-point arithmetic units for different precision requirements and thereby improving energy efficiency while maintaining manageable hardware complexity
Data Source
AI summary
A deep neural network accelerator includes a feature loader that stores input features, a weight memory that stores a weight, and a processing element. The processing element applies 1-bit weight values to the input features to generate results according to the 1-bit weight values, receives a target weight corresponding to the input features from the weight memory, and selects a target result corresponding to the received target weight from among the results to generate output features.